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-rwxr-xr-xsrc/mainboard/gizmosphere/gizmo/devicetree.cb69
1 files changed, 69 insertions, 0 deletions
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb
new file mode 100755
index 0000000000..301f79aeeb
--- /dev/null
+++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb
@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2013 Sage Electronic Engineering, LLC
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family14/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family14
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1510 inherit
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 4.0 off end # PCIE P2P bridge 0x9604
+ device pci 5.0 on end # PCIE P2P bridge 0x9605
+ device pci 6.0 off end # PCIE P2P bridge 0x9606
+ device pci 7.0 off end # PCIE P2P bridge 0x9607
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end # agesa northbridge
+
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.1 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.1 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on end # LPC 0x439d
+ device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
+ device pci 14.5 off end # USB 2
+ device pci 15.0 on end # PCIe PortA # PCIe x4 slot off of high speed edge connector
+ device pci 16.0 off end # OHCI USB3
+ device pci 16.2 off end # EHCI USB3
+ register "gpp_configuration" = "0" #4:0:0:0
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end #southbridge/amd/cimx/sb800
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/agesa/family14/root_complex