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-rw-r--r--src/mainboard/gizmosphere/gizmo/mainboard.c15
-rw-r--r--src/mainboard/gizmosphere/gizmo2/romstage.c19
2 files changed, 9 insertions, 25 deletions
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
index b65f56b074..63d94530e9 100644
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo/mainboard.c
@@ -14,12 +14,12 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/acpimmio.h>
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_ops.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
/**********************************************
* Enable the dedicated functions of the board.
@@ -30,18 +30,17 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */
- u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
- write8(misc_mem_clk_cntrl + 0, 0xFF);
- write8(misc_mem_clk_cntrl + 1, 0x00);
- write8(misc_mem_clk_cntrl + 2, 0x00);
- write8(misc_mem_clk_cntrl + 3, 0x00);
- write8(misc_mem_clk_cntrl + 4, 0x00);
+ misc_write8(0, 0xFF);
+ misc_write8(1, 0);
+ misc_write8(2, 0);
+ misc_write8(3, 0);
+ misc_write8(4, 0);
/*
* Force the onboard SATA port to GEN2 speed.
* The offboard SATA port can remain at GEN3.
*/
- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+ pm_write8(0xda, (pm_read8(0xda) & 0xfb) | 0x04);
}
static void mainboard_final(void *chip_info)
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4676199b47..6312270712 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/acpimmio.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -29,21 +30,5 @@ void board_BeforeAgesa(struct sysinfo *cb)
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
}
-
-#if 0
- /* LPC clock? Should happen before enable_serial. */
-
- /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
- int i;
- for(i = 0; i < 200000; i++)
- val = inb(0xcd6);
-#endif
-
-#if 0
- /* Was before copy_and_run. */
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
-#endif