diff options
Diffstat (limited to 'src/mainboard/google/chell/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 797865ddc8..5701dafa5b 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -54,16 +54,16 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "2" register "PortUsb20Enable[0]" = "1" # Type-C Port 1 - register "PortUsb20Enable[1]" = "1" # Type-C Port 2 - register "PortUsb20Enable[2]" = "1" # Bluetooth - register "PortUsb20Enable[4]" = "1" # Type-A Port 1 - register "PortUsb20Enable[6]" = "1" # Camera - register "PortUsb20Enable[8]" = "1" # Type-A Port 2 + register "PortUsb20Enable[1]" = "1" # Type-A Port + register "PortUsb20Enable[2]" = "1" # Camera + register "PortUsb20Enable[3]" = "1" # Bluetooth + register "PortUsb20Enable[4]" = "1" # SD + register "PortUsb20Enable[5]" = "1" # Type-C Port 2 register "PortUsb30Enable[0]" = "1" # Type-C Port 1 register "PortUsb30Enable[1]" = "1" # Type-C Port 2 - register "PortUsb30Enable[2]" = "1" # Type-A Port 1 - register "PortUsb30Enable[3]" = "1" # Type-A Port 2 + register "PortUsb30Enable[2]" = "1" # Type-A Port + register "PortUsb30Enable[3]" = "1" # SD # USB Per Port HS Preemphasis Bias register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \ |