diff options
Diffstat (limited to 'src/mainboard/google/cyan/variants/terra/ramstage.c')
| -rw-r--r-- | src/mainboard/google/cyan/variants/terra/ramstage.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c new file mode 100644 index 0000000000..6ef4360377 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/ramstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include <variant/onboard.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + uint8_t boardid = 0; + uint8_t projectid = 0; + + boardid = board_id(); + projectid = (boardid >> 3) & 0x01; + + if (projectid == TERRA2_PROJECT_ID) { + params->Usb2Port0PerPortPeTxiSet = 7; + params->Usb2Port0PerPortTxiSet = 6; + params->Usb2Port0IUsbTxEmphasisEn = 3; + params->Usb2Port0PerPortTxPeHalf = 1; + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 6; + params->Usb2Port1IUsbTxEmphasisEn = 3; + params->Usb2Port1PerPortTxPeHalf = 1; + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 6; + params->Usb2Port2IUsbTxEmphasisEn = 3; + params->Usb2Port2PerPortTxPeHalf = 1; + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 6; + params->Usb2Port3IUsbTxEmphasisEn = 3; + params->Usb2Port3PerPortTxPeHalf = 1; + params->Usb2Port4PerPortPeTxiSet = 7; + params->Usb2Port4PerPortTxiSet = 6; + params->Usb2Port4IUsbTxEmphasisEn = 3; + params->Usb2Port4PerPortTxPeHalf = 1; + } else { + params->Usb2Port0PerPortPeTxiSet = 7; + params->Usb2Port0PerPortTxiSet = 6; + params->Usb2Port0IUsbTxEmphasisEn = 3; + params->Usb2Port0PerPortTxPeHalf = 1; + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 6; + params->Usb2Port1IUsbTxEmphasisEn = 3; + params->Usb2Port1PerPortTxPeHalf = 1; + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 3; + params->Usb2Port2IUsbTxEmphasisEn = 2; + params->Usb2Port2PerPortTxPeHalf = 1; + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 6; + params->Usb2Port3IUsbTxEmphasisEn = 3; + params->Usb2Port3PerPortTxPeHalf = 1; + params->Usb2Port4PerPortPeTxiSet = 7; + params->Usb2Port4PerPortTxiSet = 3; + params->Usb2Port4IUsbTxEmphasisEn = 2; + params->Usb2Port4PerPortTxPeHalf = 1; + } +} |