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-rw-r--r--src/mainboard/google/cyan/variants/reks/Makefile.inc1
-rw-r--r--src/mainboard/google/cyan/variants/reks/romstage.c47
2 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc
index 65771247b9..db2eea3d29 100644
--- a/src/mainboard/google/cyan/variants/reks/Makefile.inc
+++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc
@@ -14,6 +14,7 @@
## GNU General Public License for more details.
##
+romstage-y += romstage.c
romstage-y += spd_util.c
ramstage-y += gpio.c
diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c
new file mode 100644
index 0000000000..5414cbd7d5
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/reks/romstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+#include <baseboard/variants.h>
+#include <mainboard/google/cyan/spd/spd_util.h>
+
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
+{
+ int ram_id = get_ramid();
+
+ /*
+ * RAMID = A - 4GiB Micron MT52L256M32D1PF-107
+ * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107
+ */
+ if (ram_id == 2 || ram_id == 0xA) {
+
+ /*
+ * For new micron part, it requires read/receive
+ * enable training before sending cmds to get MR8.
+ * To override dram geometry settings as below:
+ *
+ * PcdDramWidth = x32
+ * PcdDramDensity = 8Gb
+ * PcdDualRankDram = disable
+ */
+ memory_params->PcdRxOdtLimitChannel0 = 1;
+ memory_params->PcdRxOdtLimitChannel1 = 1;
+ memory_params->PcdDisableAutoDetectDram = 1;
+ memory_params->PcdDramWidth = 2;
+ memory_params->PcdDramDensity = 3;
+ memory_params->PcdDualRankDram = 0;
+ }
+}