diff options
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard')
5 files changed, 104 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc index 7c092e44c2..4f87de9c41 100644 --- a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c smm-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b8ceae2f8c..83922422c1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -45,6 +45,14 @@ static const struct pad_config gpio_table[] = { /* B23 : EC_AP_USB_C1_HDMI_HPD */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + /* C0 : RAM_STRAP_0 */ + PAD_CFG_GPI(GPP_C0, NONE, DEEP), + /* C3 : RAM_STRAP_1 */ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : RAM_STRAP_2 */ + PAD_CFG_GPI(GPP_C4, NONE, DEEP), + /* C5 : RAM_STRAP_3 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ @@ -113,6 +121,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : RAM_STRAP_0 */ + PAD_CFG_GPI(GPP_C0, NONE, DEEP), + /* C3 : RAM_STRAP_1 */ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : RAM_STRAP_2 */ + PAD_CFG_GPI(GPP_C4, NONE, DEEP), + /* C5 : RAM_STRAP_3 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index fe9c0c5c75..395143b666 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -18,4 +18,10 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C0 +#define GPIO_MEM_CONFIG_1 GPP_C3 +#define GPIO_MEM_CONFIG_2 GPP_C4 +#define GPIO_MEM_CONFIG_3 GPP_C5 + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 32b2c8b4e7..a0facb261d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -28,4 +28,10 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); */ int board_info_get_fw_config(uint32_t *fw_config); +/* Return memory configuration structure. */ +const struct mb_cfg *variant_memcfg_config(void); + +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c new file mode 100644 index 0000000000..bcb12959d1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/meminit_jsl.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on SoC + * the value = pin number on LPDDR4 part + */ + + .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6}, + + /* WaddleDoo uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* WaddleDoo Rcomp target values */ + .rcomp_targets = {80, 40, 40, 40, 30}, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memcfg_config(void) +{ + return &baseboard_memcfg_cfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} |