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diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
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+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/icelake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/icelake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <soc/intel/icelake/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/icelake/acpi/northbridge.asl>
+ #include <soc/intel/icelake/acpi/southbridge.asl>
+ }
+ }
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+ // Chipset specific sleep states
+ #include <soc/intel/icelake/acpi/sleepstates.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+}