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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 851248d77d..ed7eb95d0d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/cannonlake
register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
- register "usb2_ports[6]" = "USB2_PORT_EMPTY"
- register "usb2_ports[7]" = "USB2_PORT_EMPTY"
- register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
@@ -162,7 +159,6 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
- register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+