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Diffstat (limited to 'src/mainboard/google/eve/devicetree.cb')
-rw-r--r--src/mainboard/google/eve/devicetree.cb16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 37a5ff0712..f757d317ee 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -148,15 +148,15 @@ chip soc/intel/skylake
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_FLEX" # Camera
- register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_MID" # Type-A Port
- register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty