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path: root/src/mainboard/google/eve/gpio.h
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Diffstat (limited to 'src/mainboard/google/eve/gpio.h')
-rw-r--r--src/mainboard/google/eve/gpio.h208
1 files changed, 104 insertions, 104 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index 21d322275e..607486be4c 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -31,69 +31,69 @@
/* Pad configuration in ramstage */
/* Leave eSPI pins untouched from default settings */
static const struct pad_config gpio_table[] = {
-/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */
+/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP41 */
/* ESPI_IO0 */
/* ESPI_IO1 */
/* ESPI_IO2 */
/* ESPI_IO3 */
/* ESPI_CS# */
-/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
-/* PIRQA# */ PAD_CFG_NC(GPP_A7),
-/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
+/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP44 */
+/* PIRQA# */ PAD_NC(GPP_A7, NONE),
+/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP45 */
/* ESPI_CLK */
-/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
-/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
-/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
+/* PME# */ PAD_NC(GPP_A11, NONE), /* TP67 */
+/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
-/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
-/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
-/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
-/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
-/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
-/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
-
-/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */
-/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */
-/* VRALERT# */ PAD_CFG_NC(GPP_B2),
-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */
-/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
-/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5),
+/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
+/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
+/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
+
+/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP42 */
+/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* TP43 */
+/* VRALERT# */ PAD_NC(GPP_B2, NONE),
+/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */
+/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
+/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
-/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7),
-/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
-/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
-/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
-/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
+/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE),
+/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE),
+/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),
+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
+/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE),
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* SPKR */ PAD_CFG_NC(GPP_B14),
+/* SPKR */ PAD_NC(GPP_B14, NONE),
/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */
/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */
/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */
/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */
-/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
-/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
-/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
-/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22),
-/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
-
-/* SMBCLK */ PAD_CFG_NC(GPP_C0),
-/* SMBDATA */ PAD_CFG_NC(GPP_C1),
-/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
-/* SML0CLK */ PAD_CFG_NC(GPP_C3),
-/* SML0DATA */ PAD_CFG_NC(GPP_C4),
-/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
-/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE),
+/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
+/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE),
+/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
+/* SM1ALERT# */ PAD_NC(GPP_B23, NONE),
+
+/* SMBCLK */ PAD_NC(GPP_C0, NONE),
+/* SMBDATA */ PAD_NC(GPP_C1, NONE),
+/* SMBALERT# */ PAD_NC(GPP_C2, NONE),
+/* SML0CLK */ PAD_NC(GPP_C3, NONE),
+/* SML0DATA */ PAD_NC(GPP_C4, NONE),
+/* SML0ALERT# */ PAD_NC(GPP_C5, NONE),
+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K,
DEEP), /* EC_IN_RW */
-/* SM1DATA */ PAD_CFG_NC(GPP_C7),
-/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
-/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
-/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
-/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
+/* SM1DATA */ PAD_NC(GPP_C7, NONE),
+/* UART0_RXD */ PAD_NC(GPP_C8, NONE),
+/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
+/* UART0_RTS# */ PAD_NC(GPP_C10, NONE),
+/* UART0_CTS# */ PAD_NC(GPP_C11, NONE),
/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
@@ -109,59 +109,59 @@ static const struct pad_config gpio_table[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
-/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K,
DEEP), /* PCH_WP */
/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */
/* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE,
DEEP), /* TOUCHPAD_RESET */
-/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
-/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
-/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
-/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
-/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
-/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
-/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
-/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */
+/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
+/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
+/* FASHTRIG */ PAD_NC(GPP_D4, NONE),
+/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
+/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
+/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
+/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
+/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
-/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
-/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */
-/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
-/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
-/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
-/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
-/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
-/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
+/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
+/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, UP_20K, DEEP), /* EN_PP3300_DX_CAM */
+/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
+/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE),
+/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
+/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE),
+/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE),
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
+/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE),
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
-/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
-/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
-/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
-/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
-/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
-/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
-/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */
-/* SATALED# */ PAD_CFG_NC(GPP_E8),
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
+/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE),
+/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE),
+/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
+/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
+/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
+/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
+/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */
+/* SATALED# */ PAD_NC(GPP_E8, NONE),
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */
/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */
-/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
-/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */
-/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */
-/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */
-/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
+/* USB2_OC3# */ PAD_NC(GPP_E12, NONE),
+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* USB_C0_DP_HPD */
+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* USB_C1_DP_HPD */
+/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP48 */
+/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP244 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
-/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
-/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
-/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
-/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
-/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
+/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE),
+/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE),
+/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
+/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
+/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
+/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
@@ -176,8 +176,8 @@ static const struct pad_config gpio_table[] = {
DEEP), /* DISPLAY is master */
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
-/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
-/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */
+/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
+/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* TP109 */
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@@ -189,38 +189,38 @@ static const struct pad_config gpio_table[] = {
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* RSVD */ PAD_CFG_NC(GPP_F23),
+/* RSVD */ PAD_NC(GPP_F23, NONE),
-/* SD_CMD */ PAD_CFG_NC(GPP_G0),
-/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
-/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
-/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
-/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
-/* SD_CD# */ PAD_CFG_NC(GPP_G5),
-/* SD_CLK */ PAD_CFG_NC(GPP_G6),
-/* SD_WP */ PAD_CFG_NC(GPP_G7),
+/* SD_CMD */ PAD_NC(GPP_G0, NONE),
+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
+/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
+/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
+/* SD_CD# */ PAD_NC(GPP_G5, NONE),
+/* SD_CLK */ PAD_NC(GPP_G6, NONE),
+/* SD_WP */ PAD_NC(GPP_G7, NONE),
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-/* ACPRESENT */ PAD_CFG_NF(GPD1, 20K_PU, DEEP, NF1),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, UP_20K, DEEP, NF1),
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
-/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */
-/* RSVD */ PAD_CFG_NC(GPD7),
+/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP26 */
+/* RSVD */ PAD_NC(GPD7, NONE),
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */
-/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */
-/* LANPHYC */ PAD_CFG_NC(GPD11),
+/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP25 */
+/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP15 */
+/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
-/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K,
DEEP), /* PCH_WP */
-/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
/* Ensure UART pins are in native mode for H1 */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */