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Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
-rw-r--r--src/mainboard/google/glados/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index a9e816c979..7e1e6c7499 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -53,15 +53,15 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port (board)
+ register "usb2_ports[1]" = "USB2_PORT_MAX" # Type-C Port (flex)
register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port 1
register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID" # Type-A Port 2
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port (board)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port (flex)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2