diff options
Diffstat (limited to 'src/mainboard/google/hatch/variants/kohaku')
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/gpio.c | 26 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/ramstage.c | 32 |
3 files changed, 54 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 9cdff32074..6bd29737aa 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -17,4 +17,6 @@ SPD_SOURCES = LP_8G_2133 # 0b000 romstage-y += memory.c bootblock-y += gpio.c + ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375d6d..f52cc27724 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -97,8 +97,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -136,14 +134,30 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } /* - * GPIO settings before entering all sleep states + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . */ -static const struct pad_config sleep_gpio_table[] = { +static const struct pad_config default_sleep_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) { - *num = ARRAY_SIZE(sleep_gpio_table); - return sleep_gpio_table; + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c new file mode 100644 index 0000000000..9b919fccd8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} |