summaryrefslogtreecommitdiff
path: root/src/mainboard/google/nyan
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/nyan')
-rw-r--r--src/mainboard/google/nyan/Kconfig9
-rw-r--r--src/mainboard/google/nyan/bootblock.c47
-rw-r--r--src/mainboard/google/nyan/chromeos.c12
-rw-r--r--src/mainboard/google/nyan/mainboard.c177
-rw-r--r--src/mainboard/google/nyan/pmic.c7
-rw-r--r--src/mainboard/google/nyan/romstage.c86
6 files changed, 299 insertions, 39 deletions
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 652cef12e5..4a14b157c3 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
@@ -40,6 +41,14 @@ config DRAM_SIZE_MB
int
default 2048
+config DRAM_DMA_START
+ hex
+ default 0x90000000
+
+config DRAM_DMA_SIZE
+ hex
+ default 0x00100000
+
choice
prompt "BCT boot media"
default BCT_CFG_SPI
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index 49133ca55c..ca8eca42da 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -17,50 +17,47 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <device/i2c.h>
+#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/pinmux.h>
#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
#include "pmic.h"
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+
+ clock_configure_source(mselect, PLLP, 102000);
+
+ /* TODO: is the 1.333MHz correct? This may have always been bogus... */
+ clock_configure_source(i2c5, CLK_M, 1333);
+}
+
void bootblock_mainboard_init(void)
{
- clock_config();
+ set_clock_sources();
+
+ clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
+ CLK_H_I2C5 | CLK_H_APBDMA,
+ 0, CLK_V_MSELECT, 0);
- // I2C1 clock.
- pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
- PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
- // I2C1 data.
- pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
- PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
- // I2C2 clock.
- pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
- PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
- // I2C2 data.
- pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
- PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
- // I2C3 (cam) clock.
- pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
- PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
- // I2C3 (cam) data.
- pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
- PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C5 (PMU) clock.
pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
// I2C5 (PMU) data.
pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
-
- i2c_init(0);
- i2c_init(1);
- i2c_init(2);
i2c_init(4);
-
pmic_init(4);
/* SPI4 data out (MOSI) */
@@ -75,6 +72,6 @@ void bootblock_mainboard_init(void)
/* SPI4 chip select 0 */
pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX,
PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
-// spi_init();
+
tegra_spi_init(4);
}
diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c
index 5b8b9c0538..6377fb2058 100644
--- a/src/mainboard/google/nyan/chromeos.c
+++ b/src/mainboard/google/nyan/chromeos.c
@@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Write Protect: active low */
gpios->gpios[count].port = GPIO_R1_INDEX;
gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_R1_INDEX);
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(R1));
strncpy((char *)gpios->gpios[count].name, "write protect",
GPIO_MAX_NAME_LENGTH);
count++;
@@ -49,14 +49,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Lid: active high */
gpios->gpios[count].port = GPIO_R4_INDEX;
gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_R4_INDEX);
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(R4));
strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
count++;
/* Power: active low */
gpios->gpios[count].port = GPIO_Q0_INDEX;
gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_Q0_INDEX);
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0));
strncpy((char *)gpios->gpios[count].name, "power",
GPIO_MAX_NAME_LENGTH);
count++;
@@ -77,7 +77,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
- return gpio_get_in_value(GPIO_Q6_INDEX);
+ return 0;
}
int get_recovery_mode_switch(void)
@@ -85,7 +85,7 @@ int get_recovery_mode_switch(void)
uint32_t ec_events;
/* The GPIO is active low. */
- if (!gpio_get_in_value(GPIO_Q7_INDEX)) // RECMODE_GPIO
+ if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO
return 1;
ec_events = google_chromeec_get_events_b();
@@ -95,5 +95,5 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return !gpio_get_in_value(GPIO_R1_INDEX);
+ return !gpio_get_in_value(GPIO(R1));
}
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index c7258ff12d..a25c91cf5d 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -17,9 +17,47 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
#include <device/device.h>
#include <boot/coreboot_tables.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <soc/nvidia/tegra124/pmc.h>
+#include <soc/nvidia/tegra124/spi.h>
+#include <soc/nvidia/tegra124/usb.h>
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ clock_configure_source(i2c1, CLK_M, 1333);
+ clock_configure_source(i2c2, CLK_M, 1333);
+ clock_configure_source(i2c3, CLK_M, 1333);
+ clock_configure_source(i2c4, CLK_M, 1333);
+
+ clock_configure_source(sbc1, PLLP, 5000);
+
+ /*
+ * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
+ * maximum speed (48MHz) so we can change SDCLK by second stage divisor
+ * in payloads, without touching base clock.
+ */
+ clock_configure_source(sdmmc3, PLLP, 48000);
+ clock_configure_source(sdmmc4, PLLP, 48000);
+
+ /* PLLP and PLLM are switched for HOST1x for no apparent reason. */
+ write32(4 /* PLLP! */ << CLK_SOURCE_SHIFT |
+ /* TODO(rminnich): The divisor isn't accurate enough to get to
+ * 144MHz (it goes to 163 instead). What should we do here? */
+ CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000),
+ &clk_rst->clk_src_host1x);
+
+ /* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */
+ clock_configure_source(disp1, PLLC, 600000);
+}
static void setup_pinmux(void)
{
@@ -52,11 +90,139 @@ static void setup_pinmux(void)
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
+
+ // I2C1 clock.
+ pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
+ PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C1 data.
+ pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
+ PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C2 clock.
+ pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
+ PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C2 data.
+ pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
+ PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) clock.
+ pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+ PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) data.
+ pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+ PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C4 (DDC) clock.
+ pinmux_set_config(PINMUX_DDC_SCL_INDEX,
+ PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
+ // I2C4 (DDC) data.
+ pinmux_set_config(PINMUX_DDC_SDA_INDEX,
+ PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
+
+ // TODO(hungte) Revice pinmux setup, make nice little SoC functions for
+ // every single logical thing instead of dumping a wall of code below.
+ uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
+ pin_up3 = (PINMUX_PULL_UP | PINMUX_INPUT_ENABLE |
+ PINMUX_TRISTATE),
+ pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
+ pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
+
+ // MMC3
+ pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
+ PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
+ pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
+ PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
+ PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
+ PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
+ PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
+ PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
+ PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up3);
+ pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
+ PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
+
+ // MMC3 Card Detect pin.
+ gpio_input_pullup(GPIO(V2));
+ // Enable MMC power.
+ gpio_output(GPIO(R0), 1);
+
+ // MMC4
+ pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
+ PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
+ pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
+ PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
+ PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
+ PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
+ PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
+ PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
+ PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
+ PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
+ PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
+ pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
+ PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
+
+ /* TODO: This is supposed to work with the USB special function pinmux,
+ * but it doesn't. Go with GPIOs for now and solve the problem later. */
+ gpio_output_open_drain(GPIO(N4), 1); /* USB VBUS EN0 */
+ gpio_output_open_drain(GPIO(N5), 1); /* USB VBUS EN1 */
+}
+
+static void setup_kernel_info(void)
+{
+ // Setup required information for Linux kernel.
+
+ // pmc.odmdata: [18:19]: console type, [15:17]: UART id.
+ // TODO(hungte) This should be done by filling BCT values, or derived
+ // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
+ // value defined in BCT.
+ struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
+ writel(0x80080000, &pmc->odmdata);
+}
+
+static void setup_ec_spi(void)
+{
+ struct tegra_spi_channel *spi;
+
+ spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+
+ /* Set frame header for use by CrOS EC */
+ spi->frame_header = 0xec;
+ spi->rx_frame_header_enable = 1;
}
static void mainboard_init(device_t dev)
{
+ set_clock_sources();
+ clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 |
+ CLK_L_SDMMC4 | CLK_L_USBD,
+ CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
+ CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
+ CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
+ CLK_V_I2C4,
+ CLK_W_DVFS);
+
+ usb_setup_utmip1();
+ /* USB2 is the camera, we don't need it in firmware */
+ usb_setup_utmip3();
+
setup_pinmux();
+
+ i2c_init(0);
+ i2c_init(1);
+ i2c_init(2);
+ i2c_init(3);
+
+ setup_kernel_info();
+ clock_init_arm_generic_timer();
+ setup_ec_spi();
}
static void mainboard_enable(device_t dev)
@@ -68,3 +234,14 @@ struct chip_operations mainboard_ops = {
.name = "nyan",
.enable_dev = mainboard_enable,
};
+
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = CONFIG_DRAM_DMA_START;
+ dma->range_size = CONFIG_DRAM_DMA_SIZE;
+}
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
index ab951ea3a3..f52a48b8af 100644
--- a/src/mainboard/google/nyan/pmic.c
+++ b/src/mainboard/google/nyan/pmic.c
@@ -61,9 +61,14 @@ static struct pmic_write pmic_writes[] =
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
- { 0x16, 0x3f }
+ { 0x16, 0x3f },
/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+ /* panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
+ * the value (register 0x20 bit 4)
+ */
+ { 0x0c, 0x07 },
+ { 0x20, 0x10 },
};
void pmic_init(unsigned bus)
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 5a66ddeb42..a31f1f1519 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/cache.h>
+#include <arch/cpu.h>
+#include <arch/exception.h>
#include <arch/stages.h>
#include <device/device.h>
#include <cbfs.h>
@@ -25,11 +28,78 @@
#include "soc/nvidia/tegra124/chip.h"
#include <soc/display.h>
+// Convenient shorthand (in MB)
+#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
+#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
+
+enum {
+ L2CTLR_ECC_PARITY = 0x1 << 21,
+ L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
+ L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
+ L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
+ L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
+};
+
+enum {
+ L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
+ L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
+ L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
+};
+
+/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
+static void configure_l2ctlr(void)
+{
+ uint32_t val;
+
+ val = read_l2ctlr();
+ val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
+ val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
+ L2CTLR_ECC_PARITY);
+ write_l2ctlr(val);
+}
+
+/* Configures L2 Auxiliary Control Register for Cortex A15. */
+static void configure_l2actlr(void)
+{
+ uint32_t val;
+
+ val = read_l2actlr();
+ val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
+ L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
+ L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
+ write_l2actlr(val);
+}
+
void main(void)
{
- void *entry;
- const struct device *soc;
- const struct soc_nvidia_tegra124_config *config;
+ // Globally disable MMU, caches and branch prediction (these should
+ // already be disabled by default on reset).
+ uint32_t sctlr = read_sctlr();
+ sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
+ write_sctlr(sctlr);
+
+ arm_invalidate_caches();
+
+ // Renable icache and branch prediction.
+ sctlr = read_sctlr();
+ sctlr |= SCTLR_Z | SCTLR_I;
+ write_sctlr(sctlr);
+
+ configure_l2ctlr();
+ configure_l2actlr();
+
+ mmu_init();
+ mmu_config_range(0, DRAM_START, DCACHE_OFF);
+ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
+ mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
+ CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
+ mmu_disable_range(0, 1);
+ dcache_invalidate_all();
+ dcache_mmu_enable();
+
+ exception_init();
/* for quality of the user interface, it's important to get
* the video going ASAP. Because there are long delays in some
@@ -39,15 +109,17 @@ void main(void)
* early as we can in the RW stage, but never in the RO stage.
*/
- soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
+ const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc);
- if (soc && soc->chip_info){
- config = soc->chip_info;
+ if (soc && soc->chip_info) {
+ const struct soc_nvidia_tegra124_config *config =
+ soc->chip_info;
setup_display((struct soc_nvidia_tegra124_config *)config);
}
cbmem_initialize_empty();
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+ void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+ "fallback/coreboot_ram");
stage_exit(entry);
}