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-rw-r--r--src/mainboard/google/nyan/Kconfig24
-rw-r--r--src/mainboard/google/nyan/Makefile.inc5
-rw-r--r--src/mainboard/google/nyan/bootblock.c80
-rw-r--r--src/mainboard/google/nyan/chromeos.c99
-rw-r--r--src/mainboard/google/nyan/devicetree.cb48
-rw-r--r--src/mainboard/google/nyan/mainboard.c36
-rw-r--r--src/mainboard/google/nyan/pmic.c78
-rw-r--r--src/mainboard/google/nyan/pmic.h25
-rw-r--r--src/mainboard/google/nyan/romstage.c23
9 files changed, 417 insertions, 1 deletions
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 5ac58d315f..652cef12e5 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -22,6 +22,10 @@ if BOARD_GOOGLE_NYAN
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_NVIDIA_TEGRA124
+ select MAINBOARD_HAS_CHROMEOS
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
@@ -54,4 +58,24 @@ config BCT_CFG_EMMC
endchoice
+config BOOT_MEDIA_SPI_BUS
+ int "SPI bus with boot media ROM"
+ range 1 6
+ depends on BCT_CFG_SPI
+ default 4
+ help
+ Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+ int "Chip select for SPI boot media"
+ range 0 3
+ depends on BCT_CFG_SPI
+ default 0
+ help
+ Which chip select to use for boot media.
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 1
+
endif # BOARD_GOOGLE_NYAN
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index 3cf7dd249c..49ccf39ac7 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -27,6 +27,11 @@ $(obj)/generated/bct.cfg:
subdirs-y += bct
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+
romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
new file mode 100644
index 0000000000..49133ca55c
--- /dev/null
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra124/pinmux.h>
+#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
+
+#include "pmic.h"
+
+void bootblock_mainboard_init(void)
+{
+ clock_config();
+
+ // I2C1 clock.
+ pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
+ PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C1 data.
+ pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
+ PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
+ // I2C2 clock.
+ pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
+ PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C2 data.
+ pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
+ PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) clock.
+ pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+ PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) data.
+ pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+ PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C5 (PMU) clock.
+ pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
+ PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ // I2C5 (PMU) data.
+ pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
+ PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+
+ i2c_init(0);
+ i2c_init(1);
+ i2c_init(2);
+ i2c_init(4);
+
+ pmic_init(4);
+
+ /* SPI4 data out (MOSI) */
+ pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX,
+ PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 data in (MISO) */
+ pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX,
+ PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 clock */
+ pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX,
+ PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 chip select 0 */
+ pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX,
+ PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+// spi_init();
+ tegra_spi_init(4);
+}
diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c
new file mode 100644
index 0000000000..5b8b9c0538
--- /dev/null
+++ b/src/mainboard/google/nyan/chromeos.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
+#include <soc/nvidia/tegra124/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = GPIO_R1_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_R1_INDEX);
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Lid: active high */
+ gpios->gpios[count].port = GPIO_R4_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_R4_INDEX);
+ strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Power: active low */
+ gpios->gpios[count].port = GPIO_Q0_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_Q0_INDEX);
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return gpio_get_in_value(GPIO_Q6_INDEX);
+}
+
+int get_recovery_mode_switch(void)
+{
+ uint32_t ec_events;
+
+ /* The GPIO is active low. */
+ if (!gpio_get_in_value(GPIO_Q7_INDEX)) // RECMODE_GPIO
+ return 1;
+
+ ec_events = google_chromeec_get_events_b();
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get_in_value(GPIO_R1_INDEX);
+}
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 392a5ae0c1..623c5a196c 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -19,4 +19,52 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
+# N.B. We ae not using the device tree in an effective way.
+# We need to change this in future such that the on-soc
+# devices are 'chips', which will allow us to go at them
+# in parallel. This is even easier on the ARM SOCs since there
+# are no single-access resources such as the infamous
+# cf8/cfc registers found on PCs.
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "2560"
+ register "yres" = "1700"
+ register "framebuffer_bits_per_pixel" = "24"
+ register "cache_policy" = "DCACHE_WRITETHROUGH"
+
+ # With some help from the mainbaord designer
+ register "backlight_en_gpio" = "GPIO(H2)"
+ register "lvds_shutdown_gpio" = "0"
+ register "backlight_vdd_gpio" = "GPIO(P2)"
+ register "panel_vdd_gpio" = "0"
+ register "pwm" = "GPIO(H1)"
+
+# taken from u-boot; these look wrong however.
+ register "vdd_delay" = "400"
+ register "vdd_data_delay" = "4"
+ register "data_backlight_delay" = "203"
+ register "backlight_pwm_delay" = "17"
+ register "pwm_backlight_en_delay" = "15"
+
+# How to compute these: xrandr --verbose will give you this:
+#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
+# 2560 2608 2640 2720 hborder 0
+# 1700 1703 1713 1749 vborder 0
+#Then you can compute your values:
+#H front porch = 2608 - 2560 = 48
+#H sync = 2640 - 2608 = 32
+#H back porch = 2720 - 2640 = 80
+#V front porch = 1703 - 1700 = 3
+#V sync = 1713 - 1703 = 10
+#V back porch = 1749 - 1713 = 36
+#href_to_sync and vref_to_sync are from the vendor
+
+ register "href_to_sync" = "11"
+ register "hfront_porch" = "48"
+ register "hsync_width" = "32"
+ register "hback_porch" = "80"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "3"
+ register "vsync_width" = "10"
+ register "vback_porch" = "36"
end
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index 9e080214b0..c7258ff12d 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -19,10 +19,44 @@
#include <device/device.h>
#include <boot/coreboot_tables.h>
+#include <soc/nvidia/tegra124/gpio.h>
+
+static void setup_pinmux(void)
+{
+ // Write protect.
+ gpio_input_pullup(GPIO(R1));
+ // Recovery mode.
+ gpio_input_pullup(GPIO(Q7));
+ // Lid switch.
+ gpio_input_pullup(GPIO(R4));
+ // Power switch.
+ gpio_input_pullup(GPIO(Q0));
+ // Developer mode.
+ gpio_input_pullup(GPIO(Q6));
+ // EC in RW.
+ gpio_input_pullup(GPIO(U4));
+
+ // SPI1 MOSI
+ pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+ PINMUX_PULL_UP |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 MISO
+ pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+ PINMUX_PULL_UP |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 SCLK
+ pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 CS0
+ pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+}
-/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
+ setup_pinmux();
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
new file mode 100644
index 0000000000..ab951ea3a3
--- /dev/null
+++ b/src/mainboard/google/nyan/pmic.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "pmic.h"
+
+struct pmic_write
+{
+ uint8_t reg; // Register to write.
+ uint8_t val; // Value to write.
+};
+
+enum {
+ AS3722_I2C_ADDR = 0x40
+};
+
+static struct pmic_write pmic_writes[] =
+{
+ /* Don't need to set up VDD_CORE - already done - by OTP */
+
+ /* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
+ { 0x00, 0x28 },
+
+ /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+ /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+ { 0x06, 0x28 },
+
+ /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+ /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
+ { 0x12, 0x10 },
+
+ /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+
+ /*
+ * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+ * First set it to bypass 3.3V straight thru, then enable the regulator
+ *
+ * NOTE: We do this early because doing it later seems to hose the CPU
+ * power rail/partition startup. Need to debug.
+ */
+ { 0x16, 0x3f }
+
+ /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+};
+
+void pmic_init(unsigned bus)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
+ i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
+ &pmic_writes[i].val, 1);
+ udelay(10 * 1000);
+ }
+}
diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h
new file mode 100644
index 0000000000..78c9f0d7f2
--- /dev/null
+++ b/src/mainboard/google/nyan/pmic.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index c52fbd2670..5a66ddeb42 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -18,12 +18,35 @@
*/
#include <arch/stages.h>
+#include <device/device.h>
#include <cbfs.h>
+#include <cbmem.h>
#include <console/console.h>
+#include "soc/nvidia/tegra124/chip.h"
+#include <soc/display.h>
void main(void)
{
void *entry;
+ const struct device *soc;
+ const struct soc_nvidia_tegra124_config *config;
+
+ /* for quality of the user interface, it's important to get
+ * the video going ASAP. Because there are long delays in some
+ * of the powerup steps, we do some very early setup here in
+ * romstage. We don't do this in the bootblock because video
+ * setup is finicky and subject to change; hence, we do it as
+ * early as we can in the RW stage, but never in the RO stage.
+ */
+
+ soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
+ printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc);
+ if (soc && soc->chip_info){
+ config = soc->chip_info;
+ setup_display((struct soc_nvidia_tegra124_config *)config);
+ }
+
+ cbmem_initialize_empty();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
stage_exit(entry);