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-rw-r--r--src/mainboard/google/nyan/Kconfig8
-rw-r--r--src/mainboard/google/nyan/Makefile.inc4
-rw-r--r--src/mainboard/google/nyan/mainboard.c5
-rw-r--r--src/mainboard/google/nyan/memlayout.ld1
-rw-r--r--src/mainboard/google/nyan/romstage.c24
5 files changed, 21 insertions, 21 deletions
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 864e577c3d..082985d211 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -42,14 +42,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan"
-config DRAM_DMA_START
- hex
- default 0x90000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
choice
prompt "BCT boot media"
default NYAN_BCT_CFG_SPI
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index 7ac11e8a33..6506abaf6e 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -42,3 +42,7 @@ ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index b534ea908d..e52db83d18 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -268,6 +269,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/nyan/memlayout.ld b/src/mainboard/google/nyan/memlayout.ld
new file mode 100644
index 0000000000..33ce6446ad
--- /dev/null
+++ b/src/mainboard/google/nyan/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra124/memlayout.ld>
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 1ff500b5d3..f2077bbb27 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
+#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@@ -52,24 +53,25 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
- u32 dram_size = dram_end - dram_start;
+ u32 dram_start_mb = (uintptr_t)_dram/MiB;
+ u32 dram_end_mb = sdram_max_addressable_mb();
+ u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
- /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
- mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+ mmu_config_range(0, dram_start_mb, DCACHE_OFF);
+ /* SRAM is cached. MMU code will round size up to page size. */
+ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
+ DCACHE_WRITEBACK);
/* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end_mb < 4096)
+ mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();