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-rw-r--r--src/mainboard/google/nyan_big/mainboard.c2
-rw-r--r--src/mainboard/google/nyan_big/romstage.c5
2 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 5457be603c..72d348da3d 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -260,5 +260,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index b94d2dc780..2dd4c2d8bd 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -55,13 +55,14 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB,
+ DIV_ROUND_UP(REGION_SIZE(sram), MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);