diff options
Diffstat (limited to 'src/mainboard/google/samus')
38 files changed, 0 insertions, 2158 deletions
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig deleted file mode 100644 index 528a5eb409..0000000000 --- a/src/mainboard/google/samus/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -if BOARD_GOOGLE_SAMUS - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_INTEL_BROADWELL - select BOARD_ROMSIZE_KB_8192 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_PD - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select INTEL_INT15 - -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC - select LID_SWITCH - select VBOOT_EC_SLOW_UPDATE - select VBOOT_OPROM_MATTERS - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/samus - -config MAINBOARD_PART_NUMBER - string - default "Samus" - - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "samus" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "samus_pd" - -config GBB_HWID - string - depends on CHROMEOS - default "SAMUS TEST 8028" -endif diff --git a/src/mainboard/google/samus/Kconfig.name b/src/mainboard/google/samus/Kconfig.name deleted file mode 100644 index 6765d166eb..0000000000 --- a/src/mainboard/google/samus/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_SAMUS - bool "Samus" diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc deleted file mode 100644 index cc2151ca19..0000000000 --- a/src/mainboard/google/samus/Makefile.inc +++ /dev/null @@ -1,29 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c - -romstage-y += chromeos.c -ramstage-y += chromeos.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -romstage-y += pei_data.c -ramstage-y += pei_data.c - -romstage-y += board_version.c -ramstage-y += board_version.c diff --git a/src/mainboard/google/samus/acpi/ec.asl b/src/mainboard/google/samus/acpi/ec.asl deleted file mode 100644 index a7e499af89..0000000000 --- a/src/mainboard/google/samus/acpi/ec.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/samus/ec.h> - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl deleted file mode 100644 index 17f6257038..0000000000 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ /dev/null @@ -1,363 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#undef ENABLE_TOUCH_WAKE - -Scope (\_SB) -{ - Device (LID0) - { - Name (_HID, EisaId("PNP0C0D")) - Method (_LID, 0) - { - Return (\_SB.PCI0.LPCB.EC0.LIDS) - } - - // EC wake is GPIO27 which is a special DeepSX wake pin - Name (_PRW, Package(){ 0x70, 5 }) // GP27_EN - } - - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LPC Trusted Platform Module - */ -Scope (\_SB.PCI0.LPCB) -{ - #include <drivers/pc80/tpm/acpi/tpm.asl> -} - -/* - * WLAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is PCH_WLAN_WAKE_L */ - Name (GPIO, 10) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - } -} - -Scope (\_SB.PCI0.I2C0) -{ - Device (ATPB) - { - Name (_HID, "ATML0000") - Name (_DDN, "Atmel Touchpad Bootloader") - Name (_UID, 1) - Name (_S0W, 4) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x26, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - - // GPIO13 is PIRQL - Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - - Device (ATPA) - { - Name (_HID, "ATML0000") - Name (_DDN, "Atmel Touchpad") - Name (_UID, 2) - Name (_S0W, 4) - Name (ISTP, 1) /* Touchpad */ - Name (GPIO, 9) /* TRACKPAD_INT_L (WAKE) */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x4a, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - - // GPIO13 is PIRQL - Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } - }) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - - Device (CODC) - { - /* - * TODO(kane): Need official HID. - * - */ - Name (_HID, "RT5677CE") - Name (_DDN, "RT5667 Codec") - Name (_UID, 1) - Name (WAKE, 45) /* DSP_INT (use as codec wake) */ - - Name (MB1, 1) /* MICBIAS1 = 2.970V */ - Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */ - Name (DCLK, 0) /* RT5677_DMIC_CLK1 */ - Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */ - Name (IN1, 1) /* IN1 differential */ - Name (IN2, 0) /* IN2 not differential */ - Name (OUT1, 1) /* LOUT1 differential */ - Name (OUT2, 1) /* LOUT2 differential */ - Name (OUT3, 0) /* LOUT3 differential */ - Name (ASRC, 1) /* Enable I2S1 ASRC */ - Name (JD1, 0) /* JackDetect1 is not used */ - Name (JD2, 2) /* Use GPIO5 as JackDetect2 */ - Name (JD3, 3) /* Use GPIO6 as JackDetect3 */ - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "realtek,micbias1", 1 }, - Package () { "realtek,internal-dacref-en", 1 }, - Package () { "realtek,in1-differential", 1 }, - Package () { "realtek,in2-differential", 0 }, - Package () { "realtek,lout1-differential", 1 }, - Package () { "realtek,lout2-differential", 1 }, - Package () { "realtek,lout3-differential", 0 }, - Package () { "realtek,pdm_clk_div", 1 }, - Package () { "realtek,dmic2_clk_pin", 0 }, - Package () { "realtek,asrc-en", 1 }, - Package () { "realtek,jd1-gpio", 0 }, - Package () { "realtek,jd2-gpio", 2 }, - Package () { "realtek,jd3-gpio", 3 }, - Package () { "realtek,gpio-config", - Package () { 0, 0, 0, 0, 0, 2 } }, - } - }) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x2c, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - - /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */ - Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 } - - /* - * Codec GPIOs are 1-based in the schematic - * - * [0] = Jack Detect (INPUT) - * [1] = Mic Present (INPUT) - * [2] = Interrupt to the host (OUTPUT) - * [3] = Interrupt to the host (OUTPUT) - * [4] = Headphone amp control (OUTPUT) - */ - - /* Index 0: Jack Detect - PLUG_DET is GPIO5 */ - GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, - "\\_SB.PCI0.I2C0.CODC") { 4 } - - /* Index 1: Mic Present - MIC_PRESENT_L is GPIO6 */ - GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, - "\\_SB.PCI0.I2C0.CODC") { 5 } - - /* Index 2: Codec IRQ - HOTWORD_DET_L is GPIO1 */ - GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, - "\\_SB.PCI0.I2C0.CODC") { 0 } - - /* Index 3: Codec Wake - DSP_INT is GPIO4 */ - GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, - "\\_SB.PCI0.I2C0.CODC") { 3 } - - /* Index 4: Headphone amp - HP_AMP_SHDN_L is GPIO2 */ - GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly, - "\\_SB.PCI0.I2C0.CODC") { 1 } - }) - - Name (_PRW, Package() { WAKE, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^WAKE) - } - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.PCI0.I2C1) -{ - Device (ATSB) - { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen Bootloader") - Name (_UID, 4) - Name (_S0W, 4) - Name (ISTP, 0) /* TouchScreen */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x27, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C1", // ResourceSource - ) - - // GPIO14 is PIRQM - Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } - }) - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - - Device (ATSA) - { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen") - Name (_UID, 5) - Name (_S0W, 4) - Name (ISTP, 0) /* TouchScreen */ - Name (GPIO, 14) /* TOUCH_INT_L */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x4b, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C1", // ResourceSource - ) - - // GPIO14 is PIRQM - Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } - }) - -#ifdef ENABLE_TOUCH_WAKE - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } -#endif - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.PCI0.SPI0) -{ - Device (CODC) - { - // TODO: Need official HID. - Name (_HID, "RT5677AA") - Name (_UID, 1) - Name (_CRS, ResourceTemplate () - { - SpiSerialBus ( - 0, // DeviceSelection (CS0?) - PolarityLow, // DeviceSelectionPolarity - FourWireMode, // WireMode - 8, // DataBitLength - ControllerInitiated, // SlaveMode - 1000000, // ConnectionSpeed (1MHz) - ClockPolarityLow, // ClockPolarity - ClockPhaseFirst, // ClockPhase - "\\_SB.PCI0.SPI0", // ResourceSource - 0, // ResourceSourceIndex - ResourceConsumer, // ResourceUsage - ) - }) - } -} diff --git a/src/mainboard/google/samus/acpi/superio.asl b/src/mainboard/google/samus/acpi/superio.asl deleted file mode 100644 index 0504d9f1a1..0000000000 --- a/src/mainboard/google/samus/acpi/superio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/samus/ec.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/samus/acpi/thermal.asl b/src/mainboard/google/samus/acpi/thermal.asl deleted file mode 100644 index 9d494cb157..0000000000 --- a/src/mainboard/google/samus/acpi/thermal.asl +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (TCHK, 0, Serialized) - { - // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) - - // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) - Return (Local0) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for EC to re-poll - Sleep (1000) - - // Re-read temperature from EC - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - } -} diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c deleted file mode 100644 index ccca999394..0000000000 --- a/src/mainboard/google/samus/acpi_tables.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include "thermal.h" - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/mainboard/google/samus/board_info.txt b/src/mainboard/google/samus/board_info.txt deleted file mode 100644 index 3e630d3974..0000000000 --- a/src/mainboard/google/samus/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: laptop -ROM protocol: SPI -Flashrom support: y diff --git a/src/mainboard/google/samus/board_version.c b/src/mainboard/google/samus/board_version.c deleted file mode 100644 index 550ad797c4..0000000000 --- a/src/mainboard/google/samus/board_version.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/google/chromeec/ec.h> -#include "board_version.h" - -const char *samus_board_version(void) -{ - switch (google_chromeec_get_board_version()) { - case SAMUS_EC_BOARD_VERSION_EVT1: - return "EVT1"; - case SAMUS_EC_BOARD_VERSION_EVT2: - return "EVT2"; - case SAMUS_EC_BOARD_VERSION_EVT3: - return "EVT3"; - case SAMUS_EC_BOARD_VERSION_EVT4: - return "EVT4"; - default: - return "Unknown"; - } -} diff --git a/src/mainboard/google/samus/board_version.h b/src/mainboard/google/samus/board_version.h deleted file mode 100644 index f5371a19fa..0000000000 --- a/src/mainboard/google/samus/board_version.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SAMUS_BOARD_VERSION_H -#define SAMUS_BOARD_VERSION_H - -#define SAMUS_EC_BOARD_VERSION_EVT1 3 -#define SAMUS_EC_BOARD_VERSION_EVT2 4 -#define SAMUS_EC_BOARD_VERSION_EVT3 5 -#define SAMUS_EC_BOARD_VERSION_EVT4 0 - -const char *samus_board_version(void); - -#endif diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c deleted file mode 100644 index ea099f55b4..0000000000 --- a/src/mainboard/google/samus/chromeos.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> - -/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 16 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME), - CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/samus/chromeos.fmd b/src/mainboard/google/samus/chromeos.fmd deleted file mode 100644 index 0c05ce95ce..0000000000 --- a/src/mainboard/google/samus/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x6f000 - COREBOOT(CBFS)@0x70000 0x180000 - } - } - } -} diff --git a/src/mainboard/google/samus/cmos.layout b/src/mainboard/google/samus/cmos.layout deleted file mode 100644 index b575e02970..0000000000 --- a/src/mainboard/google/samus/cmos.layout +++ /dev/null @@ -1,110 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb deleted file mode 100644 index d12762d60c..0000000000 --- a/src/mainboard/google/samus/devicetree.cb +++ /dev/null @@ -1,112 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Enable DDI2 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_port0_gen3_tx" = "0x72" - register "sio_acpi_mode" = "1" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" - - # Disable S0ix for now - register "s0ix_enable" = "0" - - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 on end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl deleted file mode 100644 index 02e63637a7..0000000000 --- a/src/mainboard/google/samus/dsdt.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/broadwell/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/samus/ec.c b/src/mainboard/google/samus/ec.c deleted file mode 100644 index 2f516b1f8a..0000000000 --- a/src/mainboard/google/samus/ec.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h deleted file mode 100644 index bfcdfb3988..0000000000 --- a/src/mainboard/google/samus/ec.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -#endif diff --git a/src/mainboard/google/samus/fadt.c b/src/mainboard/google/samus/fadt.c deleted file mode 100644 index 11831bdbb3..0000000000 --- a/src/mainboard/google/samus/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h deleted file mode 100644 index 82af0e4bea..0000000000 --- a/src/mainboard/google/samus/gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SAMUS_GPIO_H -#define SAMUS_GPIO_H - -#include <soc/gpio.h> - -#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23 -#define SAMUS_GPIO_SSD_RESET_L 47 -#define SAMUS_GPIO_WLAN_DISABLE_L 42 -#define SAMUS_GPIO_LTE_DISABLE_L 59 - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ - PCH_GPIO_INPUT_INVERT, /* 9: TRACKPAD_INT_L (WAKE) */ - PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ - PCH_GPIO_UNUSED, /* 11: UNUSED */ - PCH_GPIO_UNUSED, /* 12: UNUSED */ - PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */ - PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_INPUT, /* 16: PCH_WP */ - PCH_GPIO_UNUSED, /* 17: UNUSED */ - PCH_GPIO_UNUSED, /* 18: UNUSED */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */ - PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ - PCH_GPIO_UNUSED, /* 22: UNUSED */ - PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */ - PCH_GPIO_UNUSED, /* 24: UNUSED */ - PCH_GPIO_INPUT, /* 25: EC_IN_RW */ - PCH_GPIO_UNUSED, /* 26: UNUSED */ - PCH_GPIO_ACPI_SCI, /* 27: PCH_WAKE_L */ - PCH_GPIO_UNUSED, /* 28: UNUSED */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */ - PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */ - PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ - PCH_GPIO_UNUSED, /* 42: WLAN_DISABLE_L */ - PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ - PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_ACPI_SCI, /* 45: DSP_INT - Codec Wake */ - PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */ - PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */ - PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_UNUSED, /* 49: UNUSED */ - PCH_GPIO_UNUSED, /* 50: UNUSED */ - PCH_GPIO_UNUSED, /* 51: UNUSED */ - PCH_GPIO_INPUT, /* 52: SIM_DET */ - PCH_GPIO_UNUSED, /* 53: UNUSED */ - PCH_GPIO_UNUSED, /* 54: UNUSED */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_UNUSED, /* 56: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */ - PCH_GPIO_UNUSED, /* 58: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - PCH_GPIO_UNUSED, /* 60: UNUSED */ - PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ - PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_INPUT, /* 65: RAM_ID3 */ - PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */ - PCH_GPIO_INPUT, /* 67: RAM_ID0 */ - PCH_GPIO_INPUT, /* 68: RAM_ID1 */ - PCH_GPIO_INPUT, /* 69: RAM_ID2 */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_UNUSED, /* 72: UNUSED */ - PCH_GPIO_UNUSED, /* 73: UNUSED */ - PCH_GPIO_UNUSED, /* 74: UNUSED */ - PCH_GPIO_UNUSED, /* 75: UNUSED */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_UNUSED, /* 81: UNUSED */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_NATIVE, /* 83: GSPI0_CS */ - PCH_GPIO_NATIVE, /* 84: GSPI0_CLK */ - PCH_GPIO_NATIVE, /* 85: GSPI0_MISO */ - PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/samus/hda_verb.c b/src/mainboard/google/samus/hda_verb.c deleted file mode 100644 index 5d088790a5..0000000000 --- a/src/mainboard/google/samus/hda_verb.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[0] = {}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c deleted file mode 100644 index 9fa9c57783..0000000000 --- a/src/mainboard/google/samus/mainboard.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <smbios.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "board_version.h" -#include "ec.h" - -void mainboard_suspend_resume(void) -{ -} - -const char *smbios_mainboard_version(void) -{ - return samus_board_version(); -} - -static void mainboard_init(device_t dev) -{ - mainboard_ec_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c deleted file mode 100644 index 051653f0e6..0000000000 --- a/src/mainboard/google/samus/pei_data.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - /* DQ byte map for Samus board */ - const u8 dq_map[2][6][2] = { - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; - /* DQS CPU<>DRAM map for Samus board */ - const u8 dqs_map[2][8] = { - { 2, 0, 1, 3, 6, 4, 7, 5 }, - { 2, 1, 0, 3, 6, 5, 4, 7 } }; - - pei_data->ec_present = 1; - - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; - - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - - /* P0: HOST PORT */ - pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, - USB_PORT_BACK_PANEL); - /* P1: HOST PORT */ - pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, - USB_PORT_BACK_PANEL); - /* P2: RAIDEN */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, - USB_PORT_BACK_PANEL); - /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P4: RAIDEN */ - pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, - USB_PORT_BACK_PANEL); - /* P5: WWAN (Disabled) */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); - /* P6: CAMERA */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: BT */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - - /* P1: HOST PORT */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); - /* P2: HOST PORT */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: RAIDEN */ - pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); - /* P4: RAIDEN */ - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c deleted file mode 100644 index 2306a2942c..0000000000 --- a/src/mainboard/google/samus/romstage.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> -#include <soc/cpu.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <mainboard/google/samus/spd/spd.h> -#include <mainboard/google/samus/gpio.h> -#include <ec/google/chromeec/ec.h> -#include "board_version.h" - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data pei_data; - - post_code(0x31); - - if (rp->power_state->prev_sleep_state != ACPI_S3) - google_chromeec_kbbacklight(100); - - printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); - - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; - - /* Initalize memory */ - romstage_common(rp); - - /* Bring SSD out of reset */ - set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH); - - /* - * Enable PP3300_AUTOBAHN_EN after initial GPIO setup - * to prevent possible brownout. - */ - set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH); -} diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c deleted file mode 100644 index b0595ccd30..0000000000 --- a/src/mainboard/google/samus/smihandler.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <elog.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include "ec.h" -#include "gpio.h" - -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); - break; - } - - return cmd; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - - /* Put SSD in reset to prevent leak. */ - set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); - /* Prevent leak from standby rail to WLAN rail in S3. */ - set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - - /* Put SSD in reset to prevent leak. */ - set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); - /* Prevent leak from standby rail to WLAN rail in S5. */ - set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } - return 0; -} diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc deleted file mode 100644 index c7c8a75b2a..0000000000 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ /dev/null @@ -1,50 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -# { GPIO65, GPIO67, GPIO68, GPIO69 } -SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += empty # 0b0001 -SPD_SOURCES += empty # 0b0010 -SPD_SOURCES += empty # 0b0011 -SPD_SOURCES += empty # 0b0100 -SPD_SOURCES += empty # 0b0101 -SPD_SOURCES += samsung_4 # 0b0110 -SPD_SOURCES += empty # 0b0111 -SPD_SOURCES += hynix_4 # 0b1000 -SPD_SOURCES += empty # 0b1001 -SPD_SOURCES += samsung_8 # 0b1010 -SPD_SOURCES += empty # 0b1011 -SPD_SOURCES += hynix_8 # 0b1100 -SPD_SOURCES += hynix_16 # 0b1101 -SPD_SOURCES += empty # 0b1110 -SPD_SOURCES += elpida_16 # 0b1111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/samus/spd/elpida_16.spd.hex b/src/mainboard/google/samus/spd/elpida_16.spd.hex deleted file mode 100644 index 5594164816..0000000000 --- a/src/mainboard/google/samus/spd/elpida_16.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Elpida EDFB232A1MA -# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 -91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 42 32 33 32 41 31 4D 41 2D 47 44 2D 46 -00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_4.spd.hex b/src/mainboard/google/samus/spd/elpida_4.spd.hex deleted file mode 100644 index e73ba6201c..0000000000 --- a/src/mainboard/google/samus/spd/elpida_4.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_8.spd.hex b/src/mainboard/google/samus/spd/elpida_8.spd.hex deleted file mode 100644 index b790943fdc..0000000000 --- a/src/mainboard/google/samus/spd/elpida_8.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/empty.spd.hex b/src/mainboard/google/samus/spd/empty.spd.hex deleted file mode 100644 index 9ec39f1ba4..0000000000 --- a/src/mainboard/google/samus/spd/empty.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_16.spd.hex b/src/mainboard/google/samus/spd/hynix_16.spd.hex deleted file mode 100644 index a03d4ed464..0000000000 --- a/src/mainboard/google/samus/spd/hynix_16.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNCLTMLAR LPDDR3 -# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 -91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00 -00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_4.spd.hex b/src/mainboard/google/samus/spd/hynix_4.spd.hex deleted file mode 100644 index 93e65a70dd..0000000000 --- a/src/mainboard/google/samus/spd/hynix_4.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 -# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E -54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8.spd.hex b/src/mainboard/google/samus/spd/hynix_8.spd.hex deleted file mode 100644 index 15737e443a..0000000000 --- a/src/mainboard/google/samus/spd/hynix_8.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 -# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 -91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E -54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_4.spd.hex b/src/mainboard/google/samus/spd/samsung_4.spd.hex deleted file mode 100644 index 4b82a3a6c7..0000000000 --- a/src/mainboard/google/samus/spd/samsung_4.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 -4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_8.spd.hex b/src/mainboard/google/samus/spd/samsung_8.spd.hex deleted file mode 100644 index c0a8fca4ea..0000000000 --- a/src/mainboard/google/samus/spd/samsung_8.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 -4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c deleted file mode 100644 index 4b5e7a6d54..0000000000 --- a/src/mainboard/google/samus/spd/spd.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <endian.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <mainboard/google/samus/ec.h> -#include <mainboard/google/samus/gpio.h> -#include <mainboard/google/samus/spd/spd.h> - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - "density %d Mb\n", banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - int spd_bits[4] = { - SPD_GPIO_BIT0, - SPD_GPIO_BIT1, - SPD_GPIO_BIT2, - SPD_GPIO_BIT3 - }; - int spd_gpio[4]; - int spd_index; - size_t spd_file_len; - char *spd_file; - - spd_gpio[0] = get_gpio(spd_bits[0]); - spd_gpio[1] = get_gpio(spd_bits[1]); - spd_gpio[2] = get_gpio(spd_bits[2]); - spd_gpio[3] = get_gpio(spd_bits[3]); - - spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | - (spd_gpio[1] << 1) | spd_gpio[0]; - - printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " - "GPIO%d=%d GPIO%d=%d)\n", spd_index, - spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], - spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h deleted file mode 100644 index dbfd6a05c1..0000000000 --- a/src/mainboard/google/samus/spd/spd.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 69 -#define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 67 -#define SPD_GPIO_BIT3 65 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/samus/thermal.h b/src/mainboard/google/samus/thermal.h deleted file mode 100644 index 0908c4c750..0000000000 --- a/src/mainboard/google/samus/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 104 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif |