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Diffstat (limited to 'src/mainboard/google/slippy')
-rw-r--r--src/mainboard/google/slippy/gma.c25
-rw-r--r--src/mainboard/google/slippy/i915io.c5
-rw-r--r--src/mainboard/google/slippy/mainboard.h25
3 files changed, 51 insertions, 4 deletions
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 7c95e40667..839fa4dc2a 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -43,6 +43,7 @@
#include <cpu/x86/msr.h>
#include <edid.h>
#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
/*
* Here is the rough outline of how we bring up the display:
@@ -228,7 +229,6 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw)
}
}
-void mainboard_train_link(struct intel_dp *intel_dp);
void mainboard_train_link(struct intel_dp *intel_dp)
{
u8 read_val;
@@ -281,6 +281,29 @@ static void test_gfx(struct intel_dp *dp)
static void test_gfx(struct intel_dp *dp) {}
#endif
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
int i915lightup(unsigned int pphysbase, unsigned int pmmio,
unsigned int pgfx, unsigned int init_fb)
{
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index 7fbffb6616..aae7f29779 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -26,6 +26,7 @@
#include <delay.h>
#include <drivers/intel/gma/i915.h>
#include <arch/io.h>
+#include "mainboard.h"
/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
int index;
@@ -33,8 +34,6 @@ u32 auxout;
u8 auxin[20];
u8 msg[32];
-extern void mainboard_train_link(struct intel_dp *intel_dp);
-
/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
void runio(struct intel_dp *dp);
@@ -71,7 +70,7 @@ void runio(struct intel_dp *dp)
gtt_write(PIPECONF(dp->transcoder),0x00000000);
gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
- gtt_write(PORT_CLK_SEL(dp->port),PORT_CLK_SEL_LCPLL_1350);
+ mainboard_set_port_clk_dp(dp);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
gtt_write(DEIIR,0x00000080);
diff --git a/src/mainboard/google/slippy/mainboard.h b/src/mainboard/google/slippy/mainboard.h
new file mode 100644
index 0000000000..f47fffda2a
--- /dev/null
+++ b/src/mainboard/google/slippy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif