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Diffstat (limited to 'src/mainboard/google/volteer/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/volteer/dsdt.asl | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index af881ae859..450835db03 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -32,11 +32,17 @@ DefinitionBlock( #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } + /* Mainboard hooks */ + #include "mainboard.asl" } // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* Include Low power idle table for a short term workaround to enable + S0ix. Once cr50 pulse width is fixed, this can be removed. */ + #include <soc/intel/common/acpi/lpit.asl> + // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { |