diff options
Diffstat (limited to 'src/mainboard/google/zoombini/variants')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/baseboard/devicetree.cb | 19 | ||||
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 32 |
2 files changed, 34 insertions, 17 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 6f70dfba2a..479f28015a 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -25,11 +25,20 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 7d89b78e8b..adeedea701 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -34,11 +34,26 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Touchscreen Digitizer | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" @@ -55,13 +70,6 @@ chip soc/intel/cannonlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" - # Touchscreen Digitizer - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST_PLUS, - .rise_time_ns = 98, - .fall_time_ns = 38, - }" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" |