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path: root/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
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Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index 8d55db6934..c6e63add4e 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -18,45 +18,45 @@ static const fsp_dxio_descriptor dxio_descriptors[] = {
// NVME SSD
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = NVME_START_LANE,
- .end_logical_lane = NVME_END_LANE,
+ .start_logical_lane = 4,
+ .end_logical_lane = 5,
.device_number = 1,
.function_number = 7,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = NVME_CLKREQ,
+ .clk_req = CLK_REQ2,
.clk_pm_support = true,
},
{
// WLAN
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = WLAN_START_LANE,
- .end_logical_lane = WLAN_END_LANE,
+ .start_logical_lane = 0,
+ .end_logical_lane = 0,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = WLAN_CLKREQ,
+ .clk_req = CLK_REQ0,
.clk_pm_support = true,
},
{
// SD Reader
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = SD_START_LANE,
- .end_logical_lane = SD_END_LANE,
+ .start_logical_lane = 1,
+ .end_logical_lane = 1,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = SD_CLKREQ,
+ .clk_req = CLK_REQ1,
}
};