1 files changed, 0 insertions, 43 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 6101330a79..c3e1e42f35 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -7,37 +7,9 @@
 #include <boardid.h>
 #include <variant/gpio.h>
 
-static const struct soc_amd_gpio gpio_set_stage_reset[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
-
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
-
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
-
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
-};
-
 static const struct soc_amd_gpio gpio_set_stage_rom[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
 	/* PEN_POWER_EN - reset */
 	PAD_GPO(GPIO_5, LOW),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
 	/* EC_FCH_WAKE_L */
 	PAD_GPI(GPIO_24, PULL_UP),
 	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
@@ -46,8 +18,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
 	/* PCIE_RST1_L - Variable timings (May remove) */
 	PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
 	/* NVME_AUX_RESET_L */
 	PAD_GPO(GPIO_40, HIGH),
 	/* WIFI_AUX_RESET_L */
@@ -62,8 +32,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_GPI(GPIO_84, PULL_NONE),
 	/* CLK_REQ0_L - WIFI */
 	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
 	/* CLK_REQ1_L - SD Card */
 	PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
 	/*  RAM_ID_3  */
@@ -76,12 +44,8 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_GPI(GPIO_131, PULL_NONE),
 	/* CLK_REQ4_L - SSD */
 	PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
 	/* BIOS_FLASH_WP_ODL */
 	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 	/* USI_RESET - reset */
 	PAD_GPO(GPIO_140, HIGH),
 	/* SD_AUX_RESET_L */
@@ -207,13 +171,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 };
 
 const __weak
-struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
-{
-	*size = ARRAY_SIZE(gpio_set_stage_reset);
-	return gpio_set_stage_reset;
-}
-
-const __weak
 struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(gpio_set_stage_rom);