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-rw-r--r--src/mainboard/google/chell/devicetree.cb3
-rw-r--r--src/mainboard/google/glados/devicetree.cb3
-rw-r--r--src/mainboard/google/lars/devicetree.cb3
3 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 384d374877..3f40449f0f 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index ff145c548f..c315cd947d 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 8ecacdd267..e411ad4a2b 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -12,8 +12,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"