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-rw-r--r--src/mainboard/google/Kconfig3
-rw-r--r--src/mainboard/google/rambi/Kconfig36
-rw-r--r--src/mainboard/google/rambi/Makefile.inc24
-rw-r--r--src/mainboard/google/rambi/acpi/chromeos.asl24
-rw-r--r--src/mainboard/google/rambi/acpi/ec.asl37
-rw-r--r--src/mainboard/google/rambi/acpi/mainboard.asl28
-rw-r--r--src/mainboard/google/rambi/acpi/platform.asl73
-rw-r--r--src/mainboard/google/rambi/acpi/superio.asl20
-rw-r--r--src/mainboard/google/rambi/acpi/thermal.asl246
-rw-r--r--src/mainboard/google/rambi/acpi/video.asl43
-rw-r--r--src/mainboard/google/rambi/acpi_tables.c287
-rw-r--r--src/mainboard/google/rambi/chromeos.c79
-rw-r--r--src/mainboard/google/rambi/cmos.layout139
-rw-r--r--src/mainboard/google/rambi/devicetree.cb8
-rw-r--r--src/mainboard/google/rambi/dsdt.asl55
-rw-r--r--src/mainboard/google/rambi/fadt.c156
-rw-r--r--src/mainboard/google/rambi/gpio.c188
-rw-r--r--src/mainboard/google/rambi/mainboard.c143
-rw-r--r--src/mainboard/google/rambi/mainboard_smi.c63
-rw-r--r--src/mainboard/google/rambi/romstage.c37
-rw-r--r--src/mainboard/google/rambi/thermal.h57
21 files changed, 1746 insertions, 0 deletions
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index c866c1fec1..b86b0add59 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -40,6 +40,8 @@ config BOARD_GOOGLE_PEPPY
bool "Peppy"
config BOARD_GOOGLE_PIT
bool "Pit"
+config BOARD_GOOGLE_RAMBI
+ bool "Rambi"
config BOARD_GOOGLE_SLIPPY
bool "Slippy"
config BOARD_GOOGLE_SNOW
@@ -56,6 +58,7 @@ source "src/mainboard/google/link/Kconfig"
source "src/mainboard/google/parrot/Kconfig"
source "src/mainboard/google/peppy/Kconfig"
source "src/mainboard/google/pit/Kconfig"
+source "src/mainboard/google/rambi/Kconfig"
source "src/mainboard/google/slippy/Kconfig"
source "src/mainboard/google/snow/Kconfig"
source "src/mainboard/google/stout/Kconfig"
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
new file mode 100644
index 0000000000..4d149c9b5f
--- /dev/null
+++ b/src/mainboard/google/rambi/Kconfig
@@ -0,0 +1,36 @@
+if BOARD_GOOGLE_RAMBI
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select SOC_INTEL_BAYTRAIL
+ select ENABLE_BUILTIN_COM1
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_CHROMEOS
+ select CHROMEOS
+ select MARK_GRAPHICS_MEM_WRCOMB
+
+config MAINBOARD_DIR
+ string
+ default google/rambi
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "RAMBI"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+endif # BOARD_INTEL_BAYLEYBAY
diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc
new file mode 100644
index 0000000000..d3c6f0d700
--- /dev/null
+++ b/src/mainboard/google/rambi/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += gpio.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl
new file mode 100644
index 0000000000..40ffcf0156
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/chromeos.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+ Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery
+ Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer
+ Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/google/rambi/acpi/ec.asl b/src/mainboard/google/rambi/acpi/ec.asl
new file mode 100644
index 0000000000..9ae5951aca
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/ec.asl
@@ -0,0 +1,37 @@
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x03),
+ ACPR, 1, // AC Power (1=present)
+ , 2,
+ CFAN, 1, // CPU Fan (1=on)
+ , 2,
+ LIDS, 1, // Lid State (1=open)
+ , 1,
+ SPTR, 8, // SMBUS Protocol Register
+ SSTS, 8, // SMBUS Status Register
+ SADR, 8, // SMBUS Address Register
+ SCMD, 8, // SMBUS Command Register
+ SBFR, 256, // SMBUS Block Buffer
+ SCNT, 8, // SMBUS Block Count
+
+ Offset (0x3a),
+ ECMD, 8, // EC Command Register
+
+ Offset (0x82),
+ PECL, 8, // PECI fractional (1/64 Celsius)
+ PECH, 8, // PECI integer (Celsius)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+}
diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl
new file mode 100644
index 0000000000..3e0eb339ee
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake from deep sleep via GPIO27
+ Name(_PRW, Package(){27, 4})
+}
diff --git a/src/mainboard/google/rambi/acpi/platform.asl b/src/mainboard/google/rambi/acpi/platform.asl
new file mode 100644
index 0000000000..e0693928fa
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/platform.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl
new file mode 100644
index 0000000000..9092a6c79d
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/superio.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
diff --git a/src/mainboard/google/rambi/acpi/thermal.asl b/src/mainboard/google/rambi/acpi/thermal.asl
new file mode 100644
index 0000000000..00a8750a36
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/thermal.asl
@@ -0,0 +1,246 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 0 seconds
+ Name (_TZP, 0)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (CTOK (30))
+ }
+
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (\F0OF))
+ } Else {
+ Return (CTOK (\F0ON))
+ }
+ }
+
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (\F1OF))
+ } Else {
+ Return (CTOK (\F1ON))
+ }
+ }
+
+ Method (_AC2) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (CTOK (\F2OF))
+ } Else {
+ Return (CTOK (\F2ON))
+ }
+ }
+
+ Method (_AC3) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (CTOK (\F3OF))
+ } Else {
+ Return (CTOK (\F3ON))
+ }
+ }
+
+ Method (_AC4) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (CTOK (\F4OF))
+ } Else {
+ Return (CTOK (\F4ON))
+ }
+ }
+
+ Name (_AL0, Package () { FAN0 })
+ Name (_AL1, Package () { FAN1 })
+ Name (_AL2, Package () { FAN2 })
+ Name (_AL3, Package () { FAN3 })
+ Name (_AL4, Package () { FAN4 })
+
+ PowerResource (FNP0, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (0, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP1, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP2, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP3, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP4, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ Device (FAN0)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 0)
+ Name (_PR0, Package () { FNP0 })
+ }
+
+ Device (FAN1)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 1)
+ Name (_PR0, Package () { FNP1 })
+ }
+
+ Device (FAN2)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 2)
+ Name (_PR0, Package () { FNP2 })
+ }
+
+ Device (FAN3)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 3)
+ Name (_PR0, Package () { FNP3 })
+ }
+
+ Device (FAN4)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 4)
+ Name (_PR0, Package () { FNP4 })
+ }
+ }
+}
+
diff --git a/src/mainboard/google/rambi/acpi/video.asl b/src/mainboard/google/rambi/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
new file mode 100644
index 0000000000..3723021284
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -0,0 +1,287 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <baytrail/acpi.h>
+#include <baytrail/nvs.h>
+
+extern const unsigned char AmlCode[];
+
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->f4of = FAN4_THRESHOLD_OFF;
+ gnvs->f4on = FAN4_THRESHOLD_ON;
+ gnvs->f4pw = FAN4_PWM;
+
+ gnvs->f3of = FAN3_THRESHOLD_OFF;
+ gnvs->f3on = FAN3_THRESHOLD_ON;
+ gnvs->f3pw = FAN3_PWM;
+
+ gnvs->f2of = FAN2_THRESHOLD_OFF;
+ gnvs->f2on = FAN2_THRESHOLD_ON;
+ gnvs->f2pw = FAN2_PWM;
+
+ gnvs->f1of = FAN1_THRESHOLD_OFF;
+ gnvs->f1on = FAN1_THRESHOLD_ON;
+ gnvs->f1pw = FAN1_PWM;
+
+ gnvs->f0of = FAN0_THRESHOLD_OFF;
+ gnvs->f0on = FAN0_THRESHOLD_ON;
+ gnvs->f0pw = FAN0_PWM;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 1;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+ /* Emerald Lake has no EC (?) */
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+
+ /* Update the mem console pointer. */
+ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
+
+ acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+ global_nvs_t *gnvs;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Update GNVS pointer into CBMEM */
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (!gnvs) {
+ printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n");
+ gnvs = (global_nvs_t *)current;
+ }
+
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> %p\n", i, gnvs);
+ *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs;
+ acpi_save_gnvs((unsigned long)gnvs);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs(gnvs);
+
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_serialio_ssdt(ssdt);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c
new file mode 100644
index 0000000000..2681b3a495
--- /dev/null
+++ b/src/mainboard/google/rambi/chromeos.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+/* Compile-time settings for developer and recovery mode. */
+#define DEV_MODE_SETTING 1
+#define REC_MODE_SETTING 0
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+static void fill_lb_gpio(struct lb_gpio *gpio, int polarity,
+ const char *name, int force)
+{
+ memset(gpio, 0, sizeof(*gpio));
+ gpio->port = -1;
+ gpio->polarity = polarity;
+ if (force >= 0)
+ gpio->value = force;
+ strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio *gpio;
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ gpio = gpios->gpios;
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "write protect", 0);
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "recovery", REC_MODE_SETTING);
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "developer", DEV_MODE_SETTING);
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "lid", 1); // force open
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "power", 0);
+ fill_lb_gpio(gpio++, ACTIVE_HIGH, "oprom", oprom_is_loaded);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+ return DEV_MODE_SETTING;
+}
+
+int get_recovery_mode_switch(void)
+{
+ return REC_MODE_SETTING;
+}
+
+int get_write_protect_state(void)
+{
+ return 0;
+}
+
diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout
new file mode 100644
index 0000000000..afdd3c66ca
--- /dev/null
+++ b/src/mainboard/google/rambi/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
new file mode 100644
index 0000000000..376aab6562
--- /dev/null
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -0,0 +1,8 @@
+chip soc/intel/baytrail
+ device cpu_cluster 0 on end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 1f.0 on end # LPC Bridge
+ end
+end
diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl
new file mode 100644
index 0000000000..172aaf46fb
--- /dev/null
+++ b/src/mainboard/google/rambi/dsdt.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ //#include "acpi/thermal.asl"
+
+ //#include <soc/intel/baytrail/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/baytrail/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c
new file mode 100644
index 0000000000..9c8bd60c9c
--- /dev/null
+++ b/src/mainboard/google/rambi/fadt.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ /* FIXME: hard coded address. */
+ u16 pmbase = 0x400;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x80;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 32;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 0;
+ fadt->x_gpe0_blk.bit_width = 0;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = 0;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
new file mode 100644
index 0000000000..8393e33855
--- /dev/null
+++ b/src/mainboard/google/rambi/gpio.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <baytrail/gpio.h>
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_DEFAULT, /* GPIO 0 */
+ GPIO_DEFAULT, /* GPIO 1 */
+ GPIO_DEFAULT, /* GPIO 2 */
+ GPIO_DEFAULT, /* GPIO 3 */
+ GPIO_DEFAULT, /* GPIO 4 */
+ GPIO_DEFAULT, /* GPIO 5 */
+ GPIO_DEFAULT, /* GPIO 6 */
+ GPIO_DEFAULT, /* GPIO 7 */
+ GPIO_DEFAULT, /* GPIO 8 */
+ GPIO_DEFAULT, /* GPIO 9 */
+ GPIO_DEFAULT, /* GPIO 10 */
+ GPIO_DEFAULT, /* GPIO 11 */
+ GPIO_DEFAULT, /* GPIO 12 */
+ GPIO_DEFAULT, /* GPIO 13 */
+ GPIO_DEFAULT, /* GPIO 14 */
+ GPIO_DEFAULT, /* GPIO 15 */
+ GPIO_DEFAULT, /* GPIO 16 */
+ GPIO_DEFAULT, /* GPIO 17 */
+ GPIO_DEFAULT, /* GPIO 18 */
+ GPIO_DEFAULT, /* GPIO 19 */
+ GPIO_DEFAULT, /* GPIO 20 */
+ GPIO_DEFAULT, /* GPIO 21 */
+ GPIO_DEFAULT, /* GPIO 22 */
+ GPIO_DEFAULT, /* GPIO 23 */
+ GPIO_DEFAULT, /* GPIO 24 */
+ GPIO_DEFAULT, /* GPIO 25 */
+ GPIO_DEFAULT, /* GPIO 26 */
+ GPIO_DEFAULT, /* GPIO 27 */
+ GPIO_DEFAULT, /* GPIO 28 */
+ GPIO_DEFAULT, /* GPIO 29 */
+ GPIO_DEFAULT, /* GPIO 30 */
+ GPIO_DEFAULT, /* GPIO 31 */
+ GPIO_DEFAULT, /* GPIO 32 */
+ GPIO_DEFAULT, /* GPIO 33 */
+ GPIO_DEFAULT, /* GPIO 34 */
+ GPIO_DEFAULT, /* GPIO 35 */
+ GPIO_DEFAULT, /* GPIO 36 */
+ GPIO_DEFAULT, /* GPIO 37 */
+ GPIO_DEFAULT, /* GPIO 38 */
+ GPIO_DEFAULT, /* GPIO 39 */
+ GPIO_DEFAULT, /* GPIO 40 */
+ GPIO_DEFAULT, /* GPIO 41 */
+ GPIO_DEFAULT, /* GPIO 42 */
+ GPIO_DEFAULT, /* GPIO 43 */
+ GPIO_DEFAULT, /* GPIO 44 */
+ GPIO_DEFAULT, /* GPIO 45 */
+ GPIO_DEFAULT, /* GPIO 46 */
+ GPIO_DEFAULT, /* GPIO 47 */
+ GPIO_DEFAULT, /* GPIO 48 */
+ GPIO_DEFAULT, /* GPIO 49 */
+ GPIO_DEFAULT, /* GPIO 50 */
+ GPIO_FUNC1, /* GPIO 51 - SMBus DATA */
+ GPIO_FUNC1, /* GPIO 52 - SMBus CLK */
+ GPIO_DEFAULT, /* GPIO 53 */
+ GPIO_DEFAULT, /* GPIO 54 */
+ GPIO_DEFAULT, /* GPIO 55 */
+ GPIO_DEFAULT, /* GPIO 56 */
+ GPIO_FUNC1, /* GPIO 57 - COM1 TXD */
+ GPIO_DEFAULT, /* GPIO 58 */
+ GPIO_DEFAULT, /* GPIO 59 */
+ GPIO_DEFAULT, /* GPIO 60 */
+ GPIO_FUNC1, /* GPIO 61 - COM1 RXD */
+ GPIO_DEFAULT, /* GPIO 62 */
+ GPIO_DEFAULT, /* GPIO 63 */
+ GPIO_DEFAULT, /* GPIO 64 */
+ GPIO_DEFAULT, /* GPIO 65 */
+ GPIO_DEFAULT, /* GPIO 66 */
+ GPIO_DEFAULT, /* GPIO 67 */
+ GPIO_DEFAULT, /* GPIO 68 */
+ GPIO_DEFAULT, /* GPIO 69 */
+ GPIO_DEFAULT, /* GPIO 70 */
+ GPIO_DEFAULT, /* GPIO 71 */
+ GPIO_DEFAULT, /* GPIO 72 */
+ GPIO_DEFAULT, /* GPIO 73 */
+ GPIO_DEFAULT, /* GPIO 74 */
+ GPIO_DEFAULT, /* GPIO 75 */
+ GPIO_DEFAULT, /* GPIO 76 */
+ GPIO_DEFAULT, /* GPIO 77 */
+ GPIO_DEFAULT, /* GPIO 78 */
+ GPIO_DEFAULT, /* GPIO 79 */
+ GPIO_DEFAULT, /* GPIO 80 */
+ GPIO_DEFAULT, /* GPIO 81 */
+ GPIO_DEFAULT, /* GPIO 82 */
+ GPIO_DEFAULT, /* GPIO 83 */
+ GPIO_DEFAULT, /* GPIO 84 */
+ GPIO_DEFAULT, /* GPIO 85 */
+ GPIO_DEFAULT, /* GPIO 86 */
+ GPIO_DEFAULT, /* GPIO 87 */
+ GPIO_DEFAULT, /* GPIO 88 */
+ GPIO_DEFAULT, /* GPIO 89 */
+ GPIO_DEFAULT, /* GPIO 90 */
+ GPIO_DEFAULT, /* GPIO 91 */
+ GPIO_DEFAULT, /* GPIO 92 */
+ GPIO_DEFAULT, /* GPIO 93 */
+ GPIO_DEFAULT, /* GPIO 94 */
+ GPIO_DEFAULT, /* GPIO 95 */
+ GPIO_DEFAULT, /* GPIO 96 */
+ GPIO_DEFAULT, /* GPIO 97 */
+ GPIO_DEFAULT, /* GPIO 98 */
+ GPIO_DEFAULT, /* GPIO 99 */
+ GPIO_DEFAULT, /* GPIO 100 */
+ GPIO_DEFAULT, /* GPIO 101 */
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_DEFAULT, /* GPIO 0 */
+ GPIO_DEFAULT, /* GPIO 1 */
+ GPIO_DEFAULT, /* GPIO 2 */
+ GPIO_DEFAULT, /* GPIO 3 */
+ GPIO_DEFAULT, /* GPIO 4 */
+ GPIO_DEFAULT, /* GPIO 5 */
+ GPIO_DEFAULT, /* GPIO 6 */
+ GPIO_DEFAULT, /* GPIO 7 */
+ GPIO_DEFAULT, /* GPIO 8 */
+ GPIO_DEFAULT, /* GPIO 9 */
+ GPIO_DEFAULT, /* GPIO 10 */
+ GPIO_DEFAULT, /* GPIO 11 */
+ GPIO_DEFAULT, /* GPIO 12 */
+ GPIO_DEFAULT, /* GPIO 13 */
+ GPIO_DEFAULT, /* GPIO 14 */
+ GPIO_DEFAULT, /* GPIO 15 */
+ GPIO_DEFAULT, /* GPIO 16 */
+ GPIO_DEFAULT, /* GPIO 17 */
+ GPIO_DEFAULT, /* GPIO 18 */
+ GPIO_DEFAULT, /* GPIO 19 */
+ GPIO_DEFAULT, /* GPIO 20 */
+ GPIO_DEFAULT, /* GPIO 21 */
+ GPIO_DEFAULT, /* GPIO 22 */
+ GPIO_DEFAULT, /* GPIO 23 */
+ GPIO_DEFAULT, /* GPIO 24 */
+ GPIO_DEFAULT, /* GPIO 25 */
+ GPIO_DEFAULT, /* GPIO 26 */
+ GPIO_DEFAULT, /* GPIO 27 */
+ GPIO_DEFAULT, /* GPIO 28 */
+ GPIO_DEFAULT, /* GPIO 29 */
+ GPIO_DEFAULT, /* GPIO 30 */
+ GPIO_DEFAULT, /* GPIO 31 */
+ GPIO_DEFAULT, /* GPIO 32 */
+ GPIO_DEFAULT, /* GPIO 33 */
+ GPIO_DEFAULT, /* GPIO 34 */
+ GPIO_DEFAULT, /* GPIO 35 */
+ GPIO_DEFAULT, /* GPIO 36 */
+ GPIO_DEFAULT, /* GPIO 37 */
+ GPIO_DEFAULT, /* GPIO 38 */
+ GPIO_DEFAULT, /* GPIO 39 */
+ GPIO_DEFAULT, /* GPIO 40 */
+ GPIO_DEFAULT, /* GPIO 41 */
+ GPIO_DEFAULT, /* GPIO 42 */
+ GPIO_DEFAULT, /* GPIO 43 */
+ GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = NULL,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
new file mode 100644
index 0000000000..d2bfea3e66
--- /dev/null
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
new file mode 100644
index 0000000000..0571baf32f
--- /dev/null
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <baytrail/nvs.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ mainboard_finalized = 1;
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
new file mode 100644
index 0000000000..f8451731b8
--- /dev/null
+++ b/src/mainboard/google/rambi/romstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <console/console.h>
+#include <baytrail/mrc_wrapper.h>
+#include <baytrail/romstage.h>
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ struct mrc_params mp = {
+ .mainboard = {
+ .dram_type = DRAM_DDR3L,
+ .dram_info_location = DRAM_INFO_SPD_SMBUS,
+ .spd_addrs = { 0xa0, 0xa2 },
+ },
+ };
+ rp->mrc_params = &mp;
+ romstage_common(rp);
+}
diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h
new file mode 100644
index 0000000000..f771014215
--- /dev/null
+++ b/src/mainboard/google/rambi/thermal.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BAYLEYBAY_THERMAL_H
+#define BAYLEYBAY_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF 0
+#define FAN4_THRESHOLD_ON 0
+#define FAN4_PWM 0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF 48
+#define FAN3_THRESHOLD_ON 55
+#define FAN3_PWM 0x40
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF 52
+#define FAN2_THRESHOLD_ON 64
+#define FAN2_PWM 0x80
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF 60
+#define FAN1_THRESHOLD_ON 68
+#define FAN1_PWM 0xb0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF 66
+#define FAN0_THRESHOLD_ON 78
+#define FAN0_PWM 0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 100
+
+#endif