diff options
Diffstat (limited to 'src/mainboard/google')
27 files changed, 492 insertions, 343 deletions
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6cfec3a577..f4f98309d6 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -1,7 +1,5 @@ -if BOARD_GOOGLE_CYAN - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GOOGLE_BASEBOARD_CYAN + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC @@ -14,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_BRASWELL select HAVE_ACPI_RESUME +if BOARD_GOOGLE_BASEBOARD_CYAN + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH @@ -33,14 +33,22 @@ config MAINBOARD_DIR string default google/cyan +config VARIANT_DIR + string + default "cyan" if BOARD_GOOGLE_CYAN + config MAINBOARD_PART_NUMBER string - default "Cyan" + default "Cyan" if BOARD_GOOGLE_CYAN config MAINBOARD_VENDOR string default "Google" +config DEVICETREE + string + default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN + config VGA_BIOS_FILE string depends on VGA_BIOS @@ -61,5 +69,6 @@ config VGA_BIOS_ID config GBB_HWID string depends on CHROMEOS - default "CYAN TEST A-A 1829" -endif # BOARD_GOOGLE_CYAN + default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN + +endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index a4562d3a39..91e10c9613 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -1,2 +1,3 @@ config BOARD_GOOGLE_CYAN bool "Cyan" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 43e3c9591d..01c2a91099 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -14,17 +14,18 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c +romstage-y += spd/spd.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c -ramstage-y += boardid.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl new file mode 100644 index 0000000000..9abc91e3fa --- /dev/null +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set maxim micbias to 2.8v */ + Package () { "maxim,micbias", 3 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set ti micbias to 2.8v */ + Package () { "ti,micbias", 7 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + }) +} diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 95b6951279..d0eaadd94f 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,63 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 49 -#define DPTF_TSR0_CRITICAL 75 +/* Include Variant DPTF */ +#include <variant/acpi/dptf.asl> -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 85 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 49 -#define DPTF_TSR2_CRITICAL 75 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ - Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 2000, /* PowerLimitMinimum */ - 6200, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) - -/* Include DPTF */ +/* Include SoC DPTF */ #include <acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl index ab89841f3d..271fd0a867 100644 --- a/src/mainboard/google/cyan/acpi/ec.asl +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 7a4b0ea355..3228a31bfa 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include <onboard.h> +#include <variant/onboard.h> Scope (\_SB) { @@ -26,189 +26,6 @@ Scope (\_SB) } } -Scope (\_SB.PCI0.I2C1) -{ - Device (ETSA) - { - Name (_HID, "ELAN0001") - Name (_DDN, "Elan Touchscreen ") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - - Method(_CRS, 0x0, NotSerialized) - { - Name(BUF0,ResourceTemplate () - { - I2CSerialBus( - 0x10, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCH_IRQ - } - - } ) - Return (BUF0) - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.I2C2) -{ - /* Maxim Audio Codec */ - Device (MAXM) /* Audio Codec driver I2C */ - { - Name (_ADR, 0) - Name (_HID, AUDIO_CODEC_HID) - Name (_CID, AUDIO_CODEC_CID) - Name (_DDN, AUDIO_CODEC_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set maxim micbias to 2.8v */ - Package () { "maxim,micbias", 3 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - } ) - Return (SBUF) - } - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - Device (TISW) /* TI Switch driver I2C */ - { - Name (_ADR, 0) - Name (_HID, TI_SWITCH_HID) - Name (_CID, TI_SWITCH_CID) - Name (_DDN, TI_SWITCH_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set ti micbias to 2.8v */ - Package () { "ti,micbias", 7 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } - - } ) - Return (SBUF) - } - - Method (_STA) - { - Return (0xF) - } - } -} - -Scope (\_SB.PCI0.I2C6) -{ - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C6", /* ResourceSource */ - ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.LPEA) -{ - Name (GBUF, ResourceTemplate () - { - /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - }) -} - Scope (\_SB.GPNC) { Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts @@ -225,3 +42,6 @@ Scope (\_SB.GPNC) { } } + +/* Variant-specific I2C devices */ +#include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index f2a7fc0296..ca973d0fab 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -16,7 +16,7 @@ /* mainboard configuration */ #include <ec.h> -#include <onboard.h> +#include <variant/onboard.h> #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl new file mode 100644 index 0000000000..7100120585 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name(BUF0,ResourceTemplate () + { + I2CSerialBus( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCH_IRQ + } + + } ) + Return (BUF0) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl new file mode 100644 index 0000000000..f89e1bc23f --- /dev/null +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C6", /* ResourceSource */ + ) + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index d4271e5e99..a0da53f52c 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -15,19 +15,9 @@ */ #include <arch/acpi.h> -#include <arch/acpigen.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> #include <soc/acpi.h> -#include <soc/iomap.h> #include <soc/nvs.h> -#include <string.h> -#include <types.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt index 8815b3674e..98f3d76533 100644 --- a/src/mainboard/google/cyan/board_info.txt +++ b/src/mainboard/google/cyan/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Cyan Braswell reference board +Board name: Cyan Braswell baseboard Category: laptop ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c index 15d26dc53f..5364bb9a0b 100644 --- a/src/mainboard/google/cyan/boardid.c +++ b/src/mainboard/google/cyan/boardid.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. + * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify @@ -16,7 +16,7 @@ #include <boardid.h> #include <stdlib.h> -#include "ec/google/chromeec/ec.h" +#include <ec/google/chromeec/ec.h> uint8_t board_id(void) { diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 71ba62b13e..e5ad945b90 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -15,9 +15,7 @@ * GNU General Public License for more details. */ -#include <bootstate.h> #include <device/device.h> -#include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index e247c984bd..093a49bf16 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -14,9 +14,8 @@ */ #include <soc/ramstage.h> -#include <boardid.h> -#include "onboard.h" +__attribute__ ((weak)) void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { } diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 61ebde9529..28a8a46a39 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -14,13 +14,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> -#include <lib.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> #include <soc/romstage.h> -#include <string.h> /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) @@ -33,6 +27,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) romstage_common(rp); } +__attribute__ ((weak)) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 98e4873a9b..75c1890d2c 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -25,7 +25,7 @@ #include <soc/pm.h> #include <soc/gpio.h> -#include "onboard.h" +#include <variant/onboard.h> /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 0c0d4f5651..f38fc58ff8 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -26,24 +26,10 @@ #include <soc/romstage.h> #include <string.h> #include <spd_bin.h> +#include "spd_util.h" -/* - * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz - * 0b0101 - 4GiB total - 2 x 2GiB Micro MT41K256M16TW-107 1600MHz - * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz - * 0b0111 - 2GiB total - 1 x 2GiB Micro MT41K256M16TW-107 1600MHz - */ -static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) - | (1 << 4) | (1 << 5); - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +__attribute__ ((weak)) uint8_t get_ramid(void) { - int ram_id = 0; - gpio_t spd_gpios[] = { GP_SW_80, /* SATA_GP3, RAMID0 */ GP_SW_67, /* I2C3_SCL, RAMID1 */ @@ -51,45 +37,24 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) GP_SW_64, /* I2C3_SDA, RAMID3 */ }; - ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - if (ram_id >= total_spds) - return NULL; + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + int spd_index = 0; - /* Determine if this is a single or dual channel memory system */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; + ram_id = get_ramid(); + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - /* Display the RAM type */ - switch (ram_id) { - case 0: - printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); - break; - case 2: - printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); - break; - case 1: - printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); - break; - case 3: - printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); - break; - case 4: - printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); - break; - case 5: - printk(BIOS_DEBUG, "4GiB Micro MT41K256M16TW-107 1600MHz\n"); - break; - case 6: - printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); - break; - case 7: - printk(BIOS_DEBUG, "2GiB Micro MT41K256M16TW-107 1600MHz\n"); - break; + spd_index = get_variant_spd_index(ram_id, dual); + if (spd_index >= total_spds) { + printk(BIOS_ERR, "SPD index > total SPDs\n"); + return NULL; } - /* Return the serial product data for the RAM */ - return &spd_file_content[SPD_PAGE_LEN * ram_id]; + return &spd_file_content[SPD_PAGE_LEN * spd_index]; } /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h new file mode 100644 index 0000000000..11d6eaa16d --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_UTIL_H +#define SPD_UTIL_H + +uint8_t get_ramid(void); +int get_variant_spd_index(int ram_id, int *dual); + +#endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index f5960863ae..ea80446156 100644 --- a/src/mainboard/google/cyan/spd/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -14,7 +14,9 @@ ## GNU General Public License for more details. ## -romstage-y += spd.c +romstage-y += spd_util.c + +ramstage-y += gpio.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/cyan/board_info.txt b/src/mainboard/google/cyan/variants/cyan/board_info.txt new file mode 100644 index 0000000000..b1138cadac --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb index 0454650c68..0454650c68 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/variants/cyan/devicetree.cb diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index f35b07e518..9e8c5d126b 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "irqroute.h" +#include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> #include <stdlib.h> diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..3c8dbe4a52 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 85 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ + Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2000, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..e9b16fcf78 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan touchscreen */ +#include <acpi/touchscreen_elan.asl> + +/* Elan trackpad */ +#include <acpi/trackpad_elan.asl> + +/* Maxim audio codec */ +#include <acpi/codec_maxim.asl> diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index c891aa8690..a27e47d511 100644 --- a/src/mainboard/google/cyan/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -17,7 +17,7 @@ #ifndef ONBOARD_H #define ONBOARD_H -#include "irqroute.h" +#include <mainboard/google/cyan/irqroute.h> /* * Calculation of gpio based irq. @@ -53,7 +53,7 @@ #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) #define BOARD_TOUCHSCREEN_I2C_BUS 0 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 /* SD CARD gpio */ @@ -64,12 +64,12 @@ #define AUDIO_CODEC_DDN "Maxim 98090 Codec " #define AUDIO_CODEC_I2C_ADDR 0x10 -#define TI_SWITCH_HID "104C227E" -#define TI_SWITCH_CID "104C227E" -#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " #define TI_SWITCH_I2C_ADDR 0x3B -#endif - #define DPTF_CPU_PASSIVE 88 #define DPTF_CPU_CRITICAL 90 + +#endif diff --git a/src/mainboard/google/cyan/variants/cyan/spd_util.c b/src/mainboard/google/cyan/variants/cyan/spd_util.c new file mode 100644 index 0000000000..63a1df3760 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/spd_util.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0101 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0111 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz + */ + +int get_variant_spd_index(int ram_id, int *dual) +{ + /* Determine if single or dual channel memory system */ + /* RAMID1 is deterministic for cyan */ + *dual = ((ram_id > 1) & 0x1) ? 0 : 1; + + /* Display the RAM type */ + switch (ram_id) { + case 0: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; + case 1: + printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; + case 2: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; + case 3: + printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; + case 4: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 5: + printk(BIOS_DEBUG, "4GiB Micron MT41K256M16TW-107 1600MHz\n"); + break; + case 6: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 7: + printk(BIOS_DEBUG, "2GiB Micron MT41K256M16TW-107 1600MHz\n"); + break; + } + + /* 1:1 mapping between ram_id and spd_index for cyan */ + return ram_id; +} |