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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb4
-rw-r--r--src/mainboard/google/hatch/variants/duffy/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/faffy/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/kaisa/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/noibat/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/puff/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/wyvern/overridetree.cb3
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb3
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb3
10 files changed, 10 insertions, 21 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index e9daf0d00d..4011693d34 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -30,7 +30,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
@@ -418,7 +417,7 @@ chip soc/intel/cannonlake
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index cb314ab6a2..a12b71cfbd 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -29,8 +29,6 @@ chip soc/intel/cannonlake
register "satapwroptimize" = "1"
# Enable System Agent dynamic frequency
register "SaGv" = "SaGv_Enabled"
- # Enable heci communication
- register "HeciEnabled" = "0"
# Enable Speed Shift Technology support
register "speed_shift_enable" = "1"
# Enable S0ix
@@ -312,7 +310,7 @@ chip soc/intel/cannonlake
device pci 15.1 on end # I2C #1
device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 2f2b643951..7f75c78e26 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -369,6 +367,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index 8aff8d192d..c1c44a69e9 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -376,6 +374,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 01691ff16c..67e62e7d08 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -369,6 +367,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index cac7516000..2de90ec8e2 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -284,6 +282,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index c78364dc9e..7ead982c08 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -308,6 +306,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index c394977f6e..d7b2298a06 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -303,6 +301,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index f22c6262fd..bacc6dceb7 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -15,7 +15,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[2]" = "1"
@@ -350,7 +349,7 @@ chip soc/intel/cannonlake
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 1a8e62454b..e79a8a5aeb 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -15,7 +15,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[0]" = "1"
@@ -369,7 +368,7 @@ chip soc/intel/cannonlake
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection