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-rw-r--r--src/mainboard/google/kahlee/mptable.c2
-rw-r--r--src/mainboard/google/link/mainboard.c2
-rw-r--r--src/mainboard/google/link/romstage.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
index 0cda7f7676..428e5751f8 100644
--- a/src/mainboard/google/kahlee/mptable.c
+++ b/src/mainboard/google/kahlee/mptable.c
@@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 4919e6baed..6c896fcc55 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -151,7 +151,7 @@ static void mainboard_init(struct device *dev)
/* If running on proto1 - enable reversion of gpio11. */
u32 gpio_inv;
u16 gpio_base = pci_read_config16
- (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) &
+ (pcidev_on_root(0x1f, 0), GPIO_BASE) &
0xfffc;
u16 gpio_inv_addr = gpio_base + GPI_INV;
gpio_inv = inl(gpio_inv_addr);
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index b8c13a1a19..73d33a3a12 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -39,7 +39,7 @@ void pch_enable_lpc(void)
const struct device *lpc;
const struct southbridge_intel_bd82x6x_config *config = NULL;
- lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ lpc = pcidev_on_root(0x1f, 0);
if (!lpc)
return;
if (lpc->chip_info)