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-rw-r--r--src/mainboard/google/daisy/mainboard.c4
-rw-r--r--src/mainboard/google/gale/mainboard.c2
-rw-r--r--src/mainboard/google/gale/mmu.c2
-rw-r--r--src/mainboard/google/gru/romstage.c3
-rw-r--r--src/mainboard/google/nyan/mainboard.c2
-rw-r--r--src/mainboard/google/nyan/romstage.c5
-rw-r--r--src/mainboard/google/nyan_big/mainboard.c2
-rw-r--r--src/mainboard/google/nyan_big/romstage.c5
-rw-r--r--src/mainboard/google/nyan_blaze/mainboard.c2
-rw-r--r--src/mainboard/google/nyan_blaze/romstage.c5
-rw-r--r--src/mainboard/google/peach_pit/mainboard.c4
-rw-r--r--src/mainboard/google/storm/mainboard.c2
-rw-r--r--src/mainboard/google/storm/mmu.c2
-rw-r--r--src/mainboard/google/urara/mainboard.c2
-rw-r--r--src/mainboard/google/veyron/mainboard.c2
-rw-r--r--src/mainboard/google/veyron/romstage.c2
-rw-r--r--src/mainboard/google/veyron_mickey/mainboard.c2
-rw-r--r--src/mainboard/google/veyron_mickey/romstage.c2
-rw-r--r--src/mainboard/google/veyron_rialto/mainboard.c2
-rw-r--r--src/mainboard/google/veyron_rialto/romstage.c2
20 files changed, 29 insertions, 25 deletions
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index 52cb329af6..e812189923 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -326,7 +326,7 @@ static void mainboard_enable(struct device *dev)
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_mmu_enable();
@@ -353,5 +353,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index 3a69fa2ae7..9e1a0f31e2 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -78,7 +78,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
if (IS_ENABLED(CONFIG_CHROMEOS)) {
/* Retrieve the switch interface MAC addresses. */
diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c
index 4b0ffec301..bf46f7a0d9 100644
--- a/src/mainboard/google/gale/mmu.c
+++ b/src/mainboard/google/gale/mmu.c
@@ -29,7 +29,7 @@
/* DMA memory for drivers */
#define DMA_START ((uintptr_t)_dma_coherent / MiB)
-#define DMA_SIZE (_dma_coherent_size / MiB)
+#define DMA_SIZE (REGION_SIZE(dma_coherent) / MiB)
void setup_dram_mappings(enum dram_state dram)
{
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index edf440d00e..0b944febc5 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -74,5 +74,6 @@ void platform_romstage_main(void)
mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB,
CACHED_MEM);
- mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
+ mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent),
+ UNCACHED_MEM);
}
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index b447a4a897..47d6fb2f00 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -262,5 +262,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index b94d2dc780..2dd4c2d8bd 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -55,13 +55,14 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB,
+ DIV_ROUND_UP(REGION_SIZE(sram), MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 5457be603c..72d348da3d 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -260,5 +260,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index b94d2dc780..2dd4c2d8bd 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -55,13 +55,14 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB,
+ DIV_ROUND_UP(REGION_SIZE(sram), MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c
index 6b448cba10..446bd533a8 100644
--- a/src/mainboard/google/nyan_blaze/mainboard.c
+++ b/src/mainboard/google/nyan_blaze/mainboard.c
@@ -260,5 +260,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index e44381f238..30278f9614 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -57,7 +57,8 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB,
+ DIV_ROUND_UP(REGION_SIZE(sram), MiB),
DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)
@@ -70,7 +71,7 @@ static void __attribute__((noinline)) romstage(void)
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
/*
* A watchdog reset only resets part of the system so it ends up in
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 10f150645b..a2df5f52f3 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -462,7 +462,7 @@ static void mainboard_enable(struct device *dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
@@ -487,5 +487,5 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c
index 05f982173b..b5dbbeadb4 100644
--- a/src/mainboard/google/storm/mainboard.c
+++ b/src/mainboard/google/storm/mainboard.c
@@ -122,7 +122,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c
index ba773c57a8..9750cc16e8 100644
--- a/src/mainboard/google/storm/mmu.c
+++ b/src/mainboard/google/storm/mmu.c
@@ -27,7 +27,7 @@
/* DMA memory for drivers */
#define DMA_START ((uintptr_t)_dma_coherent / MiB)
-#define DMA_SIZE (_dma_coherent_size / MiB)
+#define DMA_SIZE (REGION_SIZE(dma_coherent) / MiB)
void setup_dram_mappings(enum dram_state dram)
{
diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c
index b5c1b7dc31..d7ed51e584 100644
--- a/src/mainboard/google/urara/mainboard.c
+++ b/src/mainboard/google/urara/mainboard.c
@@ -47,7 +47,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c
index e435758ccb..230c0081cc 100644
--- a/src/mainboard/google/veyron/mainboard.c
+++ b/src/mainboard/google/veyron/mainboard.c
@@ -126,7 +126,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
void mainboard_power_on_backlight(void)
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 1d85ee3eed..9d410492b6 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -102,7 +102,7 @@ void main(void)
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
cbmem_initialize_empty();
diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c
index 74e52caf36..4b69cb17b9 100644
--- a/src/mainboard/google/veyron_mickey/mainboard.c
+++ b/src/mainboard/google/veyron_mickey/mainboard.c
@@ -105,7 +105,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
void mainboard_power_on_backlight(void)
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index 2262bae6e7..31c3596a6a 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -93,7 +93,7 @@ void main(void)
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
cbmem_initialize_empty();
diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c
index 40914ef540..e3aa9017c1 100644
--- a/src/mainboard/google/veyron_rialto/mainboard.c
+++ b/src/mainboard/google/veyron_rialto/mainboard.c
@@ -111,7 +111,7 @@ void lb_board(struct lb_header *header)
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
+ dma->range_size = REGION_SIZE(dma_coherent);
}
void mainboard_power_on_backlight(void)
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index f32bf3abf1..4dd7e0cc0f 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -103,7 +103,7 @@ void main(void)
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
+ REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
cbmem_initialize_empty();
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 15:15:13 +0000