summaryrefslogtreecommitdiff
path: root/src/mainboard/hp/8770w
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/hp/8770w')
-rw-r--r--src/mainboard/hp/8770w/Kconfig51
-rw-r--r--src/mainboard/hp/8770w/Kconfig.name2
-rw-r--r--src/mainboard/hp/8770w/Makefile.inc19
-rw-r--r--src/mainboard/hp/8770w/acpi/ec.asl16
-rw-r--r--src/mainboard/hp/8770w/acpi/platform.asl27
-rw-r--r--src/mainboard/hp/8770w/acpi/superio.asl16
-rw-r--r--src/mainboard/hp/8770w/acpi_tables.c25
-rw-r--r--src/mainboard/hp/8770w/board_info.txt7
-rw-r--r--src/mainboard/hp/8770w/cmos.default5
-rw-r--r--src/mainboard/hp/8770w/cmos.layout109
-rw-r--r--src/mainboard/hp/8770w/devicetree.cb104
-rw-r--r--src/mainboard/hp/8770w/dsdt.asl44
-rw-r--r--src/mainboard/hp/8770w/early_init.c60
-rw-r--r--src/mainboard/hp/8770w/gpio.c241
-rw-r--r--src/mainboard/hp/8770w/hda_verb.c40
-rw-r--r--src/mainboard/hp/8770w/mainboard.c25
16 files changed, 0 insertions, 791 deletions
diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig
deleted file mode 100644
index a80860c178..0000000000
--- a/src/mainboard/hp/8770w/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
-# Copyright (C) 2018 Robert Reeves
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-if BOARD_HP_8770W
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select BOARD_ROMSIZE_KB_16384
- select EC_HP_KBC1126
- select HAVE_ACPI_RESUME
- select HAVE_ACPI_TABLES
- select HAVE_CMOS_DEFAULT
- select HAVE_OPTION_TABLE
- select MAINBOARD_USES_IFD_GBE_REGION
- select NORTHBRIDGE_INTEL_SANDYBRIDGE
- select SERIRQ_CONTINUOUS_MODE
- select SOUTHBRIDGE_INTEL_C216
- select SUPERIO_SMSC_LPC47N217
- select SYSTEM_TYPE_LAPTOP
- select USE_NATIVE_RAMINIT
-
-config MAINBOARD_DIR
- string
- default "hp/8770w"
-
-config MAINBOARD_PART_NUMBER
- string
- default "EliteBook 8770w"
-
-config MAX_CPUS
- int
- default 8
-
-config USBDEBUG_HCD_INDEX
- int
- default 2
-
-endif
diff --git a/src/mainboard/hp/8770w/Kconfig.name b/src/mainboard/hp/8770w/Kconfig.name
deleted file mode 100644
index df9981c0b9..0000000000
--- a/src/mainboard/hp/8770w/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_HP_8770W
- bool "EliteBook 8770w"
diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc
deleted file mode 100644
index f4b387abed..0000000000
--- a/src/mainboard/hp/8770w/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-y += gpio.c
-romstage-y += gpio.c
-bootblock-y += early_init.c
-romstage-y += early_init.c
diff --git a/src/mainboard/hp/8770w/acpi/ec.asl b/src/mainboard/hp/8770w/acpi/ec.asl
deleted file mode 100644
index ac65fb399f..0000000000
--- a/src/mainboard/hp/8770w/acpi/ec.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/hp/kbc1126/acpi/ec.asl>
diff --git a/src/mainboard/hp/8770w/acpi/platform.asl b/src/mainboard/hp/8770w/acpi/platform.asl
deleted file mode 100644
index fe0f936a61..0000000000
--- a/src/mainboard/hp/8770w/acpi/platform.asl
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Method(_WAK,1)
-{
- \_SB.PCI0.LPCB.EC0.ACPI = 1
- \_SB.PCI0.LPCB.EC0.SLPT = 0
-
- Return(Package(){0,0})
-}
-
-Method(_PTS,1)
-{
- \_SB.PCI0.LPCB.EC0.SLPT = Arg0
-}
diff --git a/src/mainboard/hp/8770w/acpi/superio.asl b/src/mainboard/hp/8770w/acpi/superio.asl
deleted file mode 100644
index b3ea115115..0000000000
--- a/src/mainboard/hp/8770w/acpi/superio.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/8770w/acpi_tables.c b/src/mainboard/hp/8770w/acpi_tables.c
deleted file mode 100644
index b278512b46..0000000000
--- a/src/mainboard/hp/8770w/acpi_tables.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/bd82x6x/nvs.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- // the lid is open by default.
- gnvs->lids = 1;
-
- gnvs->tcrt = 100;
- gnvs->tpsv = 90;
-}
diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt
deleted file mode 100644
index 0d04ad0459..0000000000
--- a/src/mainboard/hp/8770w/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: laptop
-Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/5257511
-ROM protocol: SPI
-ROM package: SOIC-16
-ROM socketed: n
-Flashrom support: n
-Release year: 2012
diff --git a/src/mainboard/hp/8770w/cmos.default b/src/mainboard/hp/8770w/cmos.default
deleted file mode 100644
index ad822d5043..0000000000
--- a/src/mainboard/hp/8770w/cmos.default
+++ /dev/null
@@ -1,5 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-power_on_after_fail=Disable
-nmi=Enable
-sata_mode=AHCI
diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout
deleted file mode 100644
index c3ff3ef9e2..0000000000
--- a/src/mainboard/hp/8770w/cmos.layout
+++ /dev/null
@@ -1,109 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2014 Vladimir Serbinenko
-## Copyright (C) 2018 Robert Reeves
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392 3 r 0 unused
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-#400 8 r 0 reserved for century byte
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-
-421 1 e 9 sata_mode
-
-# coreboot config options: cpu
-#424 8 r 0 unused
-
-# coreboot config options: northbridge
-#435 5 r 0 unused
-
-#440 8 h 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-960 16 r 0 mrc_scrambler_seed_chk
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-9 0 AHCI
-9 1 Compatible
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 447 984
diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb
deleted file mode 100644
index 9b3f07763a..0000000000
--- a/src/mainboard/hp/8770w/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
-# Copyright (C) 2018 Robert Reeves
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-chip northbridge/intel/sandybridge
- device cpu_cluster 0x0 on
- chip cpu/intel/model_206ax
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
- device lapic 0x0 on end
- device lapic 0xacac off end
- end
- end
- device domain 0x0 on
- subsystemid 0x103c 0x176c inherit
-
- device pci 00.0 on end # Host bridge
- device pci 01.0 on # PCIe Bridge for discrete graphics
- device pci 00.0 on end # GPU
- device pci 00.1 on end # HDMI Audio on GPU
- end
- device pci 02.0 off end # Internal graphics
-
- chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
- register "c2_latency" = "0x0065"
- register "docking_supported" = "0"
- # mailbox at 0x200/0x201 and PM1 at 0x220
- register "gen1_dec" = "0x007c0201"
- register "gen2_dec" = "0x000c0101"
- register "gen3_dec" = "0x00fcfe01"
- register "gen4_dec" = "0x000402e9"
- register "gpi6_routing" = "2"
- register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
- register "sata_interface_speed_support" = "0x3"
- register "sata_port_map" = "0x1f"
- register "spi_uvscc" = "0x2005"
- register "spi_lvscc" = "0"
- register "superspeed_capable_ports" = "0x0000000f"
- register "xhci_overcurrent_mapping" = "0x00000c03"
- register "xhci_switchable_ports" = "0x0000000f"
-
- device pci 14.0 on end # USB 3.0 Controller
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 on end # Intel Gigabit Ethernet
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # HD Audio controller
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2
- device pci 1c.2 on end # Media Card and FireWire host controller
- device pci 1c.3 on end # Wireless LAN Adapter
- device pci 1c.4 on end # SATA Controller 2 for dock
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on # LPC bridge
- chip ec/hp/kbc1126
- register "ec_data_port" = "0x62"
- register "ec_cmd_port" = "0x66"
- register "ec_ctrl_reg" = "0x81"
- register "ec_fan_ctrl_value" = "0x81"
- device pnp ff.1 off end
- end
- chip superio/smsc/lpc47n217
- device pnp 4e.3 on # Parallel
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 4e.4 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.5 off end # COM2
- end
- end
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 off end # Thermal
- end
- end
-end
diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl
deleted file mode 100644
index 81f45c155e..0000000000
--- a/src/mainboard/hp/8770w/dsdt.asl
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#include <arch/acpi.h>
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0 and up
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x20141018 // OEM revision
-)
-{
- #include "acpi/platform.asl"
- #include <cpu/intel/common/acpi/cpu.asl>
- #include <southbridge/intel/common/acpi/platform.asl>
- /* global NVS and variables. */
- #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
- #include <southbridge/intel/common/acpi/sleepstates.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
- #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
- }
- }
-}
diff --git a/src/mainboard/hp/8770w/early_init.c b/src/mainboard/hp/8770w/early_init.c
deleted file mode 100644
index 6690196894..0000000000
--- a/src/mainboard/hp/8770w/early_init.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
- * Copyright (C) 2018 Robert Reeves
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <superio/smsc/lpc47n217/lpc47n217.h>
-#include <ec/hp/kbc1126/ec.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 1, 0 }, /* Dock USB3.0 */
- { 1, 1, 0 }, /* Conn */
- { 1, 1, 1 }, /* USB 3.0 */
- { 1, 1, 1 }, /* USB 3.0 */
- { 1, 0, 2 }, /* Express Card */
- { 1, 0, 2 }, /* Bluetooth */
- { 0, 0, 3 },
- { 1, 0, 3 }, /* Smart Card */
- { 1, 1, 4 }, /* Fingerprint Reader */
- { 1, 1, 4 }, /* Conn (Charger) */
- { 1, 0, 5 }, /* Camera */
- { 1, 0, 5 }, /* Dock */
- { 1, 0, 6 }, /* WWAN */
- { 1, 0, 6 }, /* Conn (eSATA Combo) */
-};
-
-void bootblock_mainboard_early_init(void)
-{
- lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- kbc1126_enter_conf();
- kbc1126_mailbox_init();
- kbc1126_kbc_init();
- kbc1126_ec_init();
- kbc1126_pm1_init();
- kbc1126_exit_conf();
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[1], 0x51, id_only);
- read_spd(&spd[2], 0x52, id_only);
- read_spd(&spd[3], 0x53, id_only);
-}
diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c
deleted file mode 100644
index 84ca7f67d5..0000000000
--- a/src/mainboard/hp/8770w/gpio.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/common/gpio.h>
-
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
- .gpio0 = GPIO_MODE_GPIO,
- .gpio1 = GPIO_MODE_GPIO,
- .gpio2 = GPIO_MODE_GPIO,
- .gpio3 = GPIO_MODE_GPIO,
- .gpio4 = GPIO_MODE_GPIO,
- .gpio5 = GPIO_MODE_NATIVE,
- .gpio6 = GPIO_MODE_GPIO,
- .gpio7 = GPIO_MODE_GPIO,
- .gpio8 = GPIO_MODE_GPIO,
- .gpio9 = GPIO_MODE_NATIVE,
- .gpio10 = GPIO_MODE_GPIO,
- .gpio11 = GPIO_MODE_GPIO,
- .gpio12 = GPIO_MODE_NATIVE,
- .gpio13 = GPIO_MODE_GPIO,
- .gpio14 = GPIO_MODE_GPIO,
- .gpio15 = GPIO_MODE_GPIO,
- .gpio16 = GPIO_MODE_GPIO,
- .gpio17 = GPIO_MODE_GPIO,
- .gpio18 = GPIO_MODE_NATIVE,
- .gpio19 = GPIO_MODE_GPIO,
- .gpio20 = GPIO_MODE_NATIVE,
- .gpio21 = GPIO_MODE_GPIO,
- .gpio22 = GPIO_MODE_GPIO,
- .gpio23 = GPIO_MODE_GPIO,
- .gpio24 = GPIO_MODE_GPIO,
- .gpio25 = GPIO_MODE_NATIVE,
- .gpio26 = GPIO_MODE_NATIVE,
- .gpio27 = GPIO_MODE_GPIO,
- .gpio28 = GPIO_MODE_GPIO,
- .gpio29 = GPIO_MODE_GPIO,
- .gpio30 = GPIO_MODE_NATIVE,
- .gpio31 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
- .gpio0 = GPIO_DIR_OUTPUT,
- .gpio1 = GPIO_DIR_INPUT,
- .gpio2 = GPIO_DIR_OUTPUT,
- .gpio3 = GPIO_DIR_INPUT,
- .gpio4 = GPIO_DIR_INPUT,
- .gpio6 = GPIO_DIR_INPUT,
- .gpio7 = GPIO_DIR_INPUT,
- .gpio8 = GPIO_DIR_INPUT,
- .gpio10 = GPIO_DIR_INPUT,
- .gpio11 = GPIO_DIR_OUTPUT,
- .gpio13 = GPIO_DIR_INPUT,
- .gpio14 = GPIO_DIR_INPUT,
- .gpio15 = GPIO_DIR_INPUT,
- .gpio16 = GPIO_DIR_INPUT,
- .gpio17 = GPIO_DIR_OUTPUT,
- .gpio19 = GPIO_DIR_INPUT,
- .gpio21 = GPIO_DIR_INPUT,
- .gpio22 = GPIO_DIR_OUTPUT,
- .gpio23 = GPIO_DIR_INPUT,
- .gpio24 = GPIO_DIR_OUTPUT,
- .gpio27 = GPIO_DIR_OUTPUT,
- .gpio28 = GPIO_DIR_OUTPUT,
- .gpio29 = GPIO_DIR_OUTPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
- .gpio0 = GPIO_LEVEL_LOW,
- .gpio2 = GPIO_LEVEL_LOW,
- .gpio11 = GPIO_LEVEL_LOW,
- .gpio17 = GPIO_LEVEL_HIGH,
- .gpio22 = GPIO_LEVEL_HIGH,
- .gpio24 = GPIO_LEVEL_HIGH,
- .gpio27 = GPIO_LEVEL_LOW,
- .gpio28 = GPIO_LEVEL_LOW,
- .gpio29 = GPIO_LEVEL_HIGH,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_reset = {
- .gpio24 = GPIO_RESET_RSMRST,
- .gpio30 = GPIO_RESET_RSMRST,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
- .gpio1 = GPIO_INVERT,
- .gpio3 = GPIO_INVERT,
- .gpio6 = GPIO_INVERT,
- .gpio7 = GPIO_INVERT,
- .gpio13 = GPIO_INVERT,
- .gpio14 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
- .gpio32 = GPIO_MODE_NATIVE,
- .gpio33 = GPIO_MODE_GPIO,
- .gpio34 = GPIO_MODE_GPIO,
- .gpio35 = GPIO_MODE_GPIO,
- .gpio36 = GPIO_MODE_GPIO,
- .gpio37 = GPIO_MODE_GPIO,
- .gpio38 = GPIO_MODE_GPIO,
- .gpio39 = GPIO_MODE_GPIO,
- .gpio40 = GPIO_MODE_NATIVE,
- .gpio41 = GPIO_MODE_NATIVE,
- .gpio42 = GPIO_MODE_NATIVE,
- .gpio43 = GPIO_MODE_NATIVE,
- .gpio44 = GPIO_MODE_GPIO,
- .gpio45 = GPIO_MODE_NATIVE,
- .gpio46 = GPIO_MODE_GPIO,
- .gpio47 = GPIO_MODE_NATIVE,
- .gpio48 = GPIO_MODE_GPIO,
- .gpio49 = GPIO_MODE_GPIO,
- .gpio50 = GPIO_MODE_GPIO,
- .gpio51 = GPIO_MODE_GPIO,
- .gpio52 = GPIO_MODE_GPIO,
- .gpio53 = GPIO_MODE_GPIO,
- .gpio54 = GPIO_MODE_GPIO,
- .gpio55 = GPIO_MODE_GPIO,
- .gpio56 = GPIO_MODE_NATIVE,
- .gpio57 = GPIO_MODE_GPIO,
- .gpio58 = GPIO_MODE_NATIVE,
- .gpio59 = GPIO_MODE_NATIVE,
- .gpio60 = GPIO_MODE_GPIO,
- .gpio61 = GPIO_MODE_GPIO,
- .gpio62 = GPIO_MODE_NATIVE,
- .gpio63 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
- .gpio33 = GPIO_DIR_OUTPUT,
- .gpio34 = GPIO_DIR_INPUT,
- .gpio35 = GPIO_DIR_OUTPUT,
- .gpio36 = GPIO_DIR_OUTPUT,
- .gpio37 = GPIO_DIR_OUTPUT,
- .gpio38 = GPIO_DIR_INPUT,
- .gpio39 = GPIO_DIR_INPUT,
- .gpio44 = GPIO_DIR_INPUT,
- .gpio46 = GPIO_DIR_INPUT,
- .gpio48 = GPIO_DIR_INPUT,
- .gpio49 = GPIO_DIR_OUTPUT,
- .gpio50 = GPIO_DIR_INPUT,
- .gpio51 = GPIO_DIR_INPUT,
- .gpio52 = GPIO_DIR_INPUT,
- .gpio53 = GPIO_DIR_OUTPUT,
- .gpio54 = GPIO_DIR_INPUT,
- .gpio55 = GPIO_DIR_INPUT,
- .gpio57 = GPIO_DIR_OUTPUT,
- .gpio60 = GPIO_DIR_OUTPUT,
- .gpio61 = GPIO_DIR_OUTPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
- .gpio33 = GPIO_LEVEL_LOW,
- .gpio35 = GPIO_LEVEL_LOW,
- .gpio36 = GPIO_LEVEL_LOW,
- .gpio37 = GPIO_LEVEL_LOW,
- .gpio49 = GPIO_LEVEL_LOW,
- .gpio53 = GPIO_LEVEL_HIGH,
- .gpio57 = GPIO_LEVEL_HIGH,
- .gpio60 = GPIO_LEVEL_HIGH,
- .gpio61 = GPIO_LEVEL_HIGH,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
- .gpio64 = GPIO_MODE_NATIVE,
- .gpio65 = GPIO_MODE_NATIVE,
- .gpio66 = GPIO_MODE_NATIVE,
- .gpio67 = GPIO_MODE_NATIVE,
- .gpio68 = GPIO_MODE_GPIO,
- .gpio69 = GPIO_MODE_GPIO,
- .gpio70 = GPIO_MODE_GPIO,
- .gpio71 = GPIO_MODE_GPIO,
- .gpio72 = GPIO_MODE_GPIO,
- .gpio73 = GPIO_MODE_GPIO,
- .gpio74 = GPIO_MODE_GPIO,
- .gpio75 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
- .gpio68 = GPIO_DIR_OUTPUT,
- .gpio69 = GPIO_DIR_INPUT,
- .gpio70 = GPIO_DIR_OUTPUT,
- .gpio71 = GPIO_DIR_OUTPUT,
- .gpio72 = GPIO_DIR_OUTPUT,
- .gpio73 = GPIO_DIR_OUTPUT,
- .gpio74 = GPIO_DIR_OUTPUT,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
- .gpio68 = GPIO_LEVEL_HIGH,
- .gpio70 = GPIO_LEVEL_HIGH,
- .gpio71 = GPIO_LEVEL_HIGH,
- .gpio72 = GPIO_LEVEL_LOW,
- .gpio73 = GPIO_LEVEL_HIGH,
- .gpio74 = GPIO_LEVEL_HIGH,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-};
-
-const struct pch_gpio_map mainboard_gpio_map = {
- .set1 = {
- .mode = &pch_gpio_set1_mode,
- .direction = &pch_gpio_set1_direction,
- .level = &pch_gpio_set1_level,
- .blink = &pch_gpio_set1_blink,
- .invert = &pch_gpio_set1_invert,
- .reset = &pch_gpio_set1_reset,
- },
- .set2 = {
- .mode = &pch_gpio_set2_mode,
- .direction = &pch_gpio_set2_direction,
- .level = &pch_gpio_set2_level,
- .reset = &pch_gpio_set2_reset,
- },
- .set3 = {
- .mode = &pch_gpio_set3_mode,
- .direction = &pch_gpio_set3_direction,
- .level = &pch_gpio_set3_level,
- .reset = &pch_gpio_set3_reset,
- },
-};
diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c
deleted file mode 100644
index f4a83b7d13..0000000000
--- a/src/mainboard/hp/8770w/hda_verb.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- * Copyright (C) 2014 Vladimir Serbinenko
- * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
- * Copyright (C) 2018 Robert Reeves
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- 0x111d7605, /* Codec Vendor / Device ID: IDT */
- 0x103c176c, /* Subsystem ID */
- 11, /* Number of 4 dword sets */
- AZALIA_SUBVENDOR(0, 0x103c176c),
- AZALIA_PIN_CFG(0, 0x0a, 0x21011030),
- AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
- AZALIA_PIN_CFG(0, 0x0c, 0x04a11020),
- AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
- AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0),
- AZALIA_PIN_CFG(0, 0x0f, 0x2181102e),
- AZALIA_PIN_CFG(0, 0x10, 0x40f000f0),
- AZALIA_PIN_CFG(0, 0x11, 0xd5a30140),
- AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0),
- AZALIA_PIN_CFG(0, 0x20, 0x40f000f0),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c
deleted file mode 100644
index b3389e5da8..0000000000
--- a/src/mainboard/hp/8770w/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
- * Copyright (C) 2018 Robert Reeves
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-static void mainboard_enable(struct device *dev)
-{
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 14:29:14 +0000