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-rw-r--r--src/mainboard/hp/dl145_g1/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 5352ccc48c..a920cc840f 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -88,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 ((1<<1)<<8) // Not sure about these values
@@ -115,7 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- amd8111_enable_rom();
}
if (bist == 0)