diff options
Diffstat (limited to 'src/mainboard/iei/juki-511p')
| -rw-r--r-- | src/mainboard/iei/juki-511p/Config.lb | 167 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/Options.lb | 147 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/auto.c | 59 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/chip.h | 25 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/cmos.layout | 73 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/failover.c | 53 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/irq_tables.c | 103 | ||||
| -rw-r--r-- | src/mainboard/iei/juki-511p/mainboard.c | 31 |
8 files changed, 658 insertions, 0 deletions
diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb new file mode 100644 index 0000000000..53b1982fd1 --- /dev/null +++ b/src/mainboard/iei/juki-511p/Config.lb @@ -0,0 +1,167 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +default ROM_SIZE = 256 * 1024 +default ROM_SECTION_SIZE = ROM_SIZE +default ROM_SECTION_OFFSET = 0 + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +mainboardinit cpu/x86/16bit/reset16.inc +ldscript /cpu/x86/16bit/reset16.lds + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +#dir /pc80 +#config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + + device pci 12.0 on + chip superio/winbond/w83977f + device pnp 3f0.0 on # FDC + irq 0x70 = 6 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + register "com1" = "{115200}" + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + register "com2" = "{115200}" + device pnp 3f0.4 on # RTC + io 0x60 = 0x070 + irq 0x70 = 8 + end + device pnp 3f0.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Int 1 for PS/2 keyboard + irq 0x72 = 12 # Int 12 for PS/2 mouse + end + device pnp 3f0.6 off # IR + end + device pnp 3f0.7 off # GPIO1 + end + device pnp 3f0.8 off # GPIO + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard + + end + + device pci 0e.0 on end # ETH0 + device pci 13.0 on end # USB + + end + end + + chip cpu/amd/model_gx1 + end + +end + diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb new file mode 100644 index 0000000000..45a8436b32 --- /dev/null +++ b/src/mainboard/iei/juki-511p/Options.lb @@ -0,0 +1,147 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses CONFIG_UDELAY_IO +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC + +uses OBJCOPY + +uses CONFIG_CONSOLE_SERIAL8250 +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL + +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS + + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +default CONFIG_UDELAY_IO=1 +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=2 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 +default DEFAULT_CONSOLE_LOGLEVEL=8 +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +end + diff --git a/src/mainboard/iei/juki-511p/auto.c b/src/mainboard/iei/juki-511p/auto.c new file mode 100644 index 0000000000..7a628ea9b1 --- /dev/null +++ b/src/mainboard/iei/juki-511p/auto.c @@ -0,0 +1,59 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/winbond/w83977f/w83977f_early_serial.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Disable Watchdog Timer. */ + inb(0x043); + inb(0x843); + + /* Initialize RAM. */ + sdram_init(); + + /* Check RAM. */ + /* ram_check(0x00000000, 640 * 1024); */ +} diff --git a/src/mainboard/iei/juki-511p/chip.h b/src/mainboard/iei/juki-511p/chip.h new file mode 100644 index 0000000000..49a3f9e0e9 --- /dev/null +++ b/src/mainboard/iei/juki-511p/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_iei_juki_511p_ops; + +struct mainboard_iei_juki_511p_config { + int nothing; +}; diff --git a/src/mainboard/iei/juki-511p/cmos.layout b/src/mainboard/iei/juki-511p/cmos.layout new file mode 100644 index 0000000000..276ae66a01 --- /dev/null +++ b/src/mainboard/iei/juki-511p/cmos.layout @@ -0,0 +1,73 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + diff --git a/src/mainboard/iei/juki-511p/failover.c b/src/mainboard/iei/juki-511p/failover.c new file mode 100644 index 0000000000..9689f67400 --- /dev/null +++ b/src/mainboard/iei/juki-511p/failover.c @@ -0,0 +1,53 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } +normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); +cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); +fallback_image: + return bist; +} diff --git a/src/mainboard/iei/juki-511p/irq_tables.c b/src/mainboard/iei/juki-511p/irq_tables.c new file mode 100644 index 0000000000..1a1e373e02 --- /dev/null +++ b/src/mainboard/iei/juki-511p/irq_tables.c @@ -0,0 +1,103 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +#define IRQ_BITMAP_LINK0 0x0800 /* chipset's INTA# input should be routed to IRQ11 */ +#define IRQ_BITMAP_LINK1 0x0400 /* chipset's INTB# input should be routed to IRQ10 */ +#define IRQ_BITMAP_LINK2 0x0000 /* chipset's INTC# input should be routed to nothing (disabled) */ +#define IRQ_BITMAP_LINK3 0x0000 /* chipset's INTD# input should be routed to nothing (disabled) */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*2, /* There can be a total of 2 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x2, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x57, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + + .slots = { + [0] = { + .slot = 0x0, /* should be 0 when it is no real slot. My device is soldered */ + .bus = 0x00, + .devfn = (0x13<<3)|0x0, /* 0x13 is my USB OHCI */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = 0x01, /* 0x01 means its connected to INTA# input at chipset */ + .bitmap = IRQ_BITMAP_LINK0 + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = 0x02, /* 0x02 means its connected to INTB# input at chipset */ + .bitmap = IRQ_BITMAP_LINK1 + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = 0x03, /* 0x03 means its connected to INTC# input at chipset */ + .bitmap = IRQ_BITMAP_LINK2 + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = 0x04, /* 0x04 means its connected to INTD# input at chipset */ + .bitmap = IRQ_BITMAP_LINK3 + } + } + }, + + [1] = { + .slot = 0x0, /* means also "on board" */ + .bus = 0x00, + .devfn = (0x0e<<3)|0x0, /* 0x0e is my Realtek Network device */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = 0x02, /* 0x02 means its connected to INTB# input at chipset */ + .bitmap = IRQ_BITMAP_LINK1 + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = 0x03, /* 0x03 means its connected to INTC# input at chipset */ + .bitmap = IRQ_BITMAP_LINK2 + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = 0x04, /* 0x04 means its connected to INTD# input at chipset */ + .bitmap = IRQ_BITMAP_LINK3 + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = 0x01, /* 0x01 means its connected to INTA# input at chipset */ + .bitmap = IRQ_BITMAP_LINK0 + } + } + } + } +}; + +/** + * Copy the IRQ routing table to memory. + * + * @param addr Destination address (between 0xF0000...0x100000). + * @return The end address of the pirq routing table in memory. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/juki-511p/mainboard.c b/src/mainboard/iei/juki-511p/mainboard.c new file mode 100644 index 0000000000..773dd47ebf --- /dev/null +++ b/src/mainboard/iei/juki-511p/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_iei_juki_511p_ops = { + CHIP_NAME("IEI JUKI-511P Mainboard") +}; |