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-rw-r--r--src/mainboard/iei/pm-lx-800-r11/Kconfig19
-rw-r--r--src/mainboard/iei/pm-lx-800-r11/romstage.c12
2 files changed, 6 insertions, 25 deletions
diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig
index a897106e68..e443c6c8d6 100644
--- a/src/mainboard/iei/pm-lx-800-r11/Kconfig
+++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig
@@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT
int
default 7
-choice
- prompt "Core/GLIU Frequency"
- default CORE_GLIU_500_266
-
-config CORE_GLIU_500_266
- bool "500MHz / 266MHz"
-
-config CORE_GLIU_500_333
- bool "500MHz / 333MHz"
-
-config CORE_GLIU_500_400
- bool "500MHz / 400MHz"
-
-endchoice
+config PLLMSRlo
+ hex
+ default 0x07de0000
endif # BOARD_IEI_PM_LX_800_R11
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index f7566221db..2992f53c12 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#if CONFIG_CORE_GLIU_500_400
-# define PLLMSRhi 0x0000059c
-#elif CONFIG_CORE_GLIU_500_333
-# define PLLMSRhi 0x0000049c
-#else
-# define PLLMSRhi 0x0000039c
-#endif
-
-#define PLLMSRlo 0x07de000
-
#include <northbridge/amd/lx/raminit.h>
#include <northbridge/amd/lx/pll_reset.c>
#include <northbridge/amd/lx/raminit.c>
@@ -80,7 +70,7 @@ void main(unsigned long bist)
report_bist_failure(bist);
- pll_reset(1);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);