diff options
Diffstat (limited to 'src/mainboard/intel/amenia/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 125 |
1 files changed, 0 insertions, 125 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb deleted file mode 100644 index 351aa5a0de..0000000000 --- a/src/mainboard/intel/amenia/devicetree.cb +++ /dev/null @@ -1,125 +0,0 @@ -chip soc/intel/apollolake - - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp0_clkreq_pin" = "3" # wifi/bt - register "pcie_rp2_clkreq_pin" = "0" # SSD - - # GPIO for PERST_0 - # If PERST_0 is defined assign the GPIO - # If PERST_0 is not defined assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # eMMC TX DATA Delay 1# - # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400 - # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 - register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required - - # eMMC TX DATA Delay 2# - # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 - # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 - # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 - # 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode - register "emmc_tx_data_cntl2" = "0x1c1c1c00" - - # eMMC RX CMD/DATA Delay 1# - # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 - # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 - # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 - # 0x00[6:0] stands for 0 delay for SDR12/Compatibility - register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00" - - # eMMC RX CMD/DATA Delay 2# - # 0x01[17:16] stands for Rx Clock before Output Buffer - # 0x00[14:8] stands for 0 delay for Auto Tuning Mode - # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200 - register "emmc_rx_cmd_data_cntl2" = "0x1001c" - - # LPSS S0ix Enable - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable DPTF - register "dptf_enable" = "1" - - device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 on end # - SATA - device pci 13.0 off end # - PCIe-A 0 - device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 - Onboard Lan - device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 on end # - PCIe-B 0 - wifi - device pci 14.1 off end # - PCIe-B 1 - Onboard M2 Slot(Wifi/BT) - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 - device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 - device pci 19.0 on end # - SPI 0 - device pci 19.1 on end # - SPI 1 - device pci 19.2 on end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1b.0 on end # - SDCARD - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device pci 1f.1 on end # - SMBUS - end -end |