summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/bayleybay_fsp
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp')
-rw-r--r--src/mainboard/intel/bayleybay_fsp/romstage.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index 34199bd2b8..ef848faa23 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -173,4 +173,9 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
/* Initialize the Azalia Verb Tables to mainboard specific version */
UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
+
+ /* Disable 2nd DIMM on Bakersport*/
+#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP)
+ UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
+#endif
}