diff options
Diffstat (limited to 'src/mainboard/intel/d945gclf/romstage.c')
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 1441bb5597..131145cfb9 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -60,7 +60,7 @@ static void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ - printk_debug(" GPIOS..."); + printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ @@ -254,7 +254,7 @@ void real_main(unsigned long bist) report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk_debug("soft reset detected.\n"); + printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } @@ -265,17 +265,17 @@ void real_main(unsigned long bist) /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); - printk_debug("PM1_CNT: %08x\n", reg32); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { #if CONFIG_HAVE_ACPI_RESUME - printk_debug("Resume from S3 detected.\n"); + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); #else - printk_debug("Resume from S3 detected, but disabled.\n"); + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); #endif } @@ -312,7 +312,7 @@ void real_main(unsigned long bist) /* This will not work if TSEG is in place! */ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - printk_debug("TOM: 0x%08x\n", tom); + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); //ram_check(0x00100000, tom); } |