diff options
Diffstat (limited to 'src/mainboard/intel/emeraldlake2')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 24 |
2 files changed, 24 insertions, 4 deletions
diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index ae233abb33..90b40ac4bf 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -13,10 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 #select MAINBOARD_HAS_CHROMEOS -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS #select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 8528bffc03..2752778047 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -29,6 +29,7 @@ #include <superio/smsc/sio1007/chip.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -154,6 +155,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 0, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 0, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_early_init(int s3resume) { } |