diff options
Diffstat (limited to 'src/mainboard/intel/emeraldlake2')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 20 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/chromeos.c | 12 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/dsdt.asl | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/mainboard.c | 2 |
4 files changed, 14 insertions, 21 deletions
diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl deleted file mode 100644 index 9f2e54a9d0..0000000000 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index bb4ebe9f54..896f8767f8 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -91,3 +92,14 @@ int get_recovery_mode_switch(void) /* Recovery: GPIO22, active low */ return !get_gpio(22); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 8d9e281def..a31c415000 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index a0fd9e831f..654b1de476 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -28,12 +28,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } |