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-rw-r--r--src/mainboard/intel/jarrell/Kconfig39
-rw-r--r--src/mainboard/intel/jarrell/board_info.txt3
-rw-r--r--src/mainboard/intel/jarrell/cmos.layout80
-rw-r--r--src/mainboard/intel/jarrell/debug.c262
-rw-r--r--src/mainboard/intel/jarrell/devicetree.cb80
-rw-r--r--src/mainboard/intel/jarrell/irq_tables.c42
-rw-r--r--src/mainboard/intel/jarrell/jarrell_fixups.c116
-rw-r--r--src/mainboard/intel/jarrell/mptable.c238
-rw-r--r--src/mainboard/intel/jarrell/power_reset_check.c22
-rw-r--r--src/mainboard/intel/jarrell/romstage.c110
-rw-r--r--src/mainboard/intel/jarrell/watchdog.c139
11 files changed, 0 insertions, 1131 deletions
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
deleted file mode 100644
index 6ecbc870f1..0000000000
--- a/src/mainboard/intel/jarrell/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-if BOARD_INTEL_JARRELL
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MPGA604
- select NORTHBRIDGE_INTEL_E7520
- select SOUTHBRIDGE_INTEL_PXHD
- select SOUTHBRIDGE_INTEL_I82801EX
- select SUPERIO_NSC_PC87427
- select ROMCC
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select UDELAY_TSC
- select USE_WATCHDOG_ON_BOOT
- select DRIVERS_ATI_RAGEXL
- select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
- string
- default intel/jarrell
-
-config MAINBOARD_PART_NUMBER
- string
- default "Jarrell"
-
-config MAX_CPUS
- int
- default 4
-
-config IRQ_SLOT_COUNT
- int
- default 18
-
-config DIMM_MAP_LOGICAL
- hex
- default 0x0124
-
-endif # BOARD_INTEL_JARRELL
diff --git a/src/mainboard/intel/jarrell/board_info.txt b/src/mainboard/intel/jarrell/board_info.txt
deleted file mode 100644
index e62a179078..0000000000
--- a/src/mainboard/intel/jarrell/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: Jarrell (SE7520JR2)
-Category: server
-Board URL: http://www.intel.com/support/motherboards/server/se7520jr2/
diff --git a/src/mainboard/intel/jarrell/cmos.layout b/src/mainboard/intel/jarrell/cmos.layout
deleted file mode 100644
index 16c2ba447a..0000000000
--- a/src/mainboard/intel/jarrell/cmos.layout
+++ /dev/null
@@ -1,80 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 376 r 0 reserved_memory
-376 1 e 1 power_up_watchdog
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 2 hyper_threading
-397 1 e 1 pxhd_bus_speed_100
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
deleted file mode 100644
index b92a75d76c..0000000000
--- a/src/mainboard/intel/jarrell/debug.c
+++ /dev/null
@@ -1,262 +0,0 @@
-#include <spd.h>
-
-static void print_reg(unsigned char index)
-{
- unsigned char data;
-
- outb(index, 0x2e);
- data = inb(0x2f);
- print_debug("0x");
- print_debug_hex8(index);
- print_debug(": 0x");
- print_debug_hex8(data);
- print_debug("\n");
- return;
-}
-
-static void xbus_en(void)
-{
- /* select the XBUS function in the SIO */
- outb(0x07, 0x2e);
- outb(0x0f, 0x2f);
- outb(0x30, 0x2e);
- outb(0x01, 0x2f);
- return;
-}
-
-static void setup_func(unsigned char func)
-{
- /* select the function in the SIO */
- outb(0x07, 0x2e);
- outb(func, 0x2f);
- /* print out the regs */
- print_reg(0x30);
- print_reg(0x60);
- print_reg(0x61);
- print_reg(0x62);
- print_reg(0x63);
- print_reg(0x70);
- print_reg(0x71);
- print_reg(0x74);
- print_reg(0x75);
- return;
-}
-
-static void siodump(void)
-{
- int i;
- unsigned char data;
-
- print_debug("\n*** SERVER I/O REGISTERS ***\n");
- for (i=0x10; i<=0x2d; i++) {
- print_reg((unsigned char)i);
- }
-#if 0
- print_debug("\n*** XBUS REGISTERS ***\n");
- setup_func(0x0f);
- for (i=0xf0; i<=0xff; i++) {
- print_reg((unsigned char)i);
- }
-
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
- setup_func(0x03);
- print_reg(0xf0);
-
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
- setup_func(0x02);
- print_reg(0xf0);
-
-#endif
- print_debug("\n*** GPIO REGISTERS ***\n");
- setup_func(0x07);
- for (i=0xf0; i<=0xf8; i++) {
- print_reg((unsigned char)i);
- }
- print_debug("\n*** GPIO VALUES ***\n");
- data = inb(0x68a);
- print_debug("\nGPDO 4: 0x");
- print_debug_hex8(data);
- data = inb(0x68b);
- print_debug("\nGPDI 4: 0x");
- print_debug_hex8(data);
- print_debug("\n");
-
-#if 0
-
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
- setup_func(0x0a);
- print_reg(0xf0);
-
- print_debug("\n*** FAN CONTROL REGISTERS ***\n");
- setup_func(0x09);
- print_reg(0xf0);
- print_reg(0xf1);
-
- print_debug("\n*** RTC REGISTERS ***\n");
- setup_func(0x10);
- print_reg(0xf0);
- print_reg(0xf1);
- print_reg(0xf3);
- print_reg(0xf6);
- print_reg(0xf7);
- print_reg(0xfe);
- print_reg(0xff);
-
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
- setup_func(0x14);
- print_reg(0xf0);
-#endif
- return;
-}
-
-static void dump_bar14(unsigned dev)
-{
- int i;
- unsigned long bar;
-
- print_debug("BAR 14 Dump\n");
-
- bar = pci_read_config32(dev, 0x14);
- for(i = 0; i <= 0x300; i+=4) {
-#if 0
- unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- val = pci_read_config8(dev, i);
-#endif
- if((i%4)==0) {
- print_debug("\n");
- print_debug_hex16(i);
- print_debug_char(' ');
- }
- print_debug_hex32(read32(bar + i));
- print_debug_char(' ');
- }
- print_debug("\n");
-}
-
-#if 0
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
- int i;
- print_debug("\n");
- for(i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl->channel0[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- device = ctrl->channel1[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- }
-}
-#endif
-
-void dump_spd_registers(void)
-{
- unsigned device;
- device = DIMM0;
- while(device <= DIMM7) {
- int status = 0;
- int i;
- print_debug("\n");
- print_debug("dimm ");
- print_debug_hex8(device);
-
- for(i = 0; (i < 256) ; i++) {
- unsigned char byte;
- if ((i % 16) == 0) {
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- status = smbus_read_byte(device, i);
- if (status < 0) {
- print_debug("bad device: ");
- print_debug_hex8(-status);
- print_debug("\n");
- break;
- }
- print_debug_hex8(status);
- print_debug_char(' ');
- }
- device++;
- print_debug("\n");
- }
-}
-
-void dump_ipmi_registers(void)
-{
- unsigned device;
- device = 0x42;
- while(device <= 0x42) {
- int status = 0;
- int i;
- print_debug("\n");
- print_debug("ipmi ");
- print_debug_hex8(device);
-
- for(i = 0; (i < 8) ; i++) {
- unsigned char byte;
- status = smbus_read_byte(device, 2);
- if (status < 0) {
- print_debug("bad device: ");
- print_debug_hex8(-status);
- print_debug("\n");
- break;
- }
- print_debug_hex8(status);
- print_debug_char(' ');
- }
- device++;
- print_debug("\n");
- }
-}
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
deleted file mode 100644
index 501bc7ed45..0000000000
--- a/src/mainboard/intel/jarrell/devicetree.cb
+++ /dev/null
@@ -1,80 +0,0 @@
-chip northbridge/intel/e7520
- device domain 0 on
- subsystemid 0x8086 0x1079 inherit
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 01.0 on end
- device pci 02.0 on
- chip southbridge/intel/pxhd # pxhd1
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 00.2 on
- chip drivers/generic/generic
- device pci 04.0 on end
- device pci 04.1 on end
- end
- end
- device pci 00.3 on end
- end
- end
- device pci 06.0 on end
- chip southbridge/intel/i82801ex # i82801er
- device pci 1d.0 on end
- device pci 1d.1 on end
- device pci 1d.2 on end
- device pci 1d.3 off end
- device pci 1d.7 on end
- device pci 1e.0 on
- chip drivers/ati/ragexl
- device pci 0c.0 on end
- end
- end
- device pci 1f.0 on
- chip superio/nsc/pc87427
- device pnp 2e.0 off end
- device pnp 2e.2 on
-# io 0x60 = 0x2f8
-# irq 0x70 = 3
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on
-# io 0x60 = 0x3f8
-# irq 0x70 = 4
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.4 off end
- device pnp 2e.5 off end
- device pnp 2e.6 on
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end
- device pnp 2e.9 off end
- device pnp 2e.a off end
- device pnp 2e.f on end
- device pnp 2e.10 off end
- device pnp 2e.14 off end
- end
- end
- device pci 1f.1 on end
- device pci 1f.2 off end
- device pci 1f.3 on end
- device pci 1f.5 off end
- device pci 1f.6 off end
- register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
- register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
- register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
- end
- end
- device cpu_cluster 0 on
- chip cpu/intel/socket_mPGA604 # cpu 0
- device lapic 0 on end
- end
- chip cpu/intel/socket_mPGA604 # cpu 1
- device lapic 6 on end
- end
- end
-end
diff --git a/src/mainboard/intel/jarrell/irq_tables.c b/src/mainboard/intel/jarrell/irq_tables.c
deleted file mode 100644
index fdeae8cd09..0000000000
--- a/src/mainboard/intel/jarrell/irq_tables.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* PCI: Interrupt Routing Table found at 0x40114180 size = 320 */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- 0x52495024, /* u32 signature */
- 0x0100, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
- 0x00, /* u8 Bus 0 */
- 0xf8, /* u8 Device 1, Function 0 */
- 0x0000, /* u16 reserve IRQ for PCI */
- 0x8086, /* u16 Vendor */
- 0x24d0, /* Device ID */
- 0x00000000, /* u32 miniport_data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x38, /* u8 checksum - mod 256 checksum must give zero */
- { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
- {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
- {0x00, 0xe8, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
- {0x02, 0x20, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
- {0x03, 0x28, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
- {0x04, 0x60, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
- {0x02, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x04, 0x00},
- {0x02, 0x10, {{0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x05, 0x00},
- {0x02, 0x18, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}}, 0x06, 0x00},
- {0x03, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x01, 0x00},
- {0x03, 0x10, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}}, 0x02, 0x00},
- {0x03, 0x18, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x03, 0x00},
- {0x00, 0x10, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
- {0x00, 0x18, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
- {0x00, 0x20, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
- {0x00, 0x28, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
- {0x00, 0x30, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
- {0x00, 0x38, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c
deleted file mode 100644
index 90e3ff1613..0000000000
--- a/src/mainboard/intel/jarrell/jarrell_fixups.c
+++ /dev/null
@@ -1,116 +0,0 @@
-#include <arch/io.h>
-
-static void mch_reset(void)
-{
- device_t dev;
- unsigned long value, base;
- dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
- if (dev != PCI_DEV_INVALID) {
- /* I/O space is always enables */
-
- /* Set gpio base */
- pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
- base = ICH5_GPIOBASE;
-
- /* Enable GPIO Bar */
- value = pci_read_config32(dev, 0x5c);
- value |= 0x10;
- pci_write_config32(dev, 0x5c, value);
-
- /* Set GPIO 19 mux to IO usage */
- value = inl(base);
- value |= (1 <<19);
- outl(value, base);
-
- /* Pull GPIO 19 low */
- value = inl(base + 0x0c);
- value &= ~(1 << 19);
- outl(value, base + 0x0c);
- }
- return;
-}
-
-static void mainboard_set_e7520_pll(unsigned bits)
-{
- uint16_t gpio_index;
- uint8_t data;
- device_t dev;
-
- /* currently only handle the Jarrell/PC87427 case */
- dev = PC87427_GPIO_DEV;
-
-
- pnp_set_logical_device(dev);
- gpio_index = pnp_read_iobase(dev, 0x60);
-
- /* select SIO GPIO port 4, pin 2 */
- pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
- /* set to push-pull, enable output */
- pnp_write_config(dev, PC87427_GPCFG1, 0x03);
-
- /* select SIO GPIO port 4, pin 4 */
- pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
- /* set to push-pull, enable output */
- pnp_write_config(dev, PC87427_GPCFG1, 0x03);
-
- /* set gpio 42,44 signal levels */
- data = inb(gpio_index + PC87427_GPDO_4);
- if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
- print_debug("set_pllsel: correct settings detected!\n");
- return; /* settings already configured */
- } else {
- outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
- /* reset */
- print_debug("set_pllsel: settings adjusted, now resetting...\n");
- // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
- // mch_reset();
- full_reset();
- }
- return;
-}
-
-static void mainboard_set_e7520_leds(void)
-{
- uint8_t cnt;
- uint8_t data;
- device_t dev;
-
- /* currently only handle the Jarrell/PC87427 case */
- dev = PC87427_GPIO_DEV;
-
- pnp_set_logical_device(dev);
-
- /* enable */
- outb(0x30, 0x2e);
- outb(0x01, 0x2f);
- outb(0x2d, 0x2e);
- outb(0x01, 0x2f);
-
- /* Set auto mode for dimm leds and post */
- outb(0xf0,0x2e);
- outb(0x70,0x2f);
- outb(0xf4,0x2e);
- outb(0x30,0x2f);
- outb(0xf5,0x2e);
- outb(0x88,0x2f);
- outb(0xf6,0x2e);
- outb(0x00,0x2f);
- outb(0xf7,0x2e);
- outb(0x90,0x2f);
- outb(0xf8,0x2e);
- outb(0x00,0x2f);
-
- /* Turn the leds off */
- outb(0x00,0x88);
- outb(0x00,0x90);
-
- /* Disable the ports */
- outb(0xf5,0x2e);
- outb(0x00,0x2f);
- outb(0xf7,0x2e);
- outb(0x00,0x2f);
- outb(0xf4,0x2e);
- outb(0x00,0x2f);
-
- return;
-}
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
deleted file mode 100644
index 21664ceb42..0000000000
--- a/src/mainboard/intel/jarrell/mptable.c
+++ /dev/null
@@ -1,238 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- unsigned char bus_pxhd_1;
- unsigned char bus_pxhd_2;
- unsigned char bus_pxhd_3 = 0;
- unsigned char bus_pxhd_4 = 0;
- unsigned char bus_pxhd_x = 0;
- unsigned char bus_ich5r_1;
- unsigned int bus_pxhd_id;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* ich5r */
- dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
- if (dev) {
- bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
-
- bus_ich5r_1 = 4;
- }
- /* pxhd-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
- if (dev) {
- bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
-
- bus_pxhd_1 = 2;
- }
- /* pxhd-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
- if (dev) {
- bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
- bus_pxhd_2 = 3;
- }
- /* test for active riser with 2nd pxh device */
- dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
- if (dev) {
- bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
- if(bus_pxhd_id == 0x35998086) {
- bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
- /* pxhd-3 */
- dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
- if (dev) {
- bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
- if(bus_pxhd_id == 0x03298086) {
- bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
- /* pxhd-4 */
- dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
- if (dev) {
- bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
- if(bus_pxhd_id == 0x032a8086) {
- bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
- }
- }
- }
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* IOAPIC handling */
-
- smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
- {
- struct resource *res;
- device_t dev;
- /* pxhd apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x09, 0x20, res->base);
- }
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
- }
- /* pxhd apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x0a, 0x20, res->base);
- }
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
- }
-
- /* pxhd apic 5 */
- if(bus_pxhd_3) { /* Active riser pxhd */
- dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x0b, 0x20, res->base);
- }
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
- }
- }
- /* pxhd apic 6 */
- if(bus_pxhd_4) { /* active riser pxhd */
- dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x0c, 0x20, res->base);
- }
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
- }
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0a, 0x08, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0b, 0x08, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0a, 0x08, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x07, 0x08, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0b, 0x08, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x05, 0x08, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0b, 0x08, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x07, 0x08, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0b, 0x08, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- bus_isa, 0x0a, 0x08, 0x10);
-
- /* Standard local interrupt assignments */
- mptable_lintsrc(mc, bus_isa);
-
- /* FIXME verify I have the irqs handled for all of the risers */
-
- /* 2:3.0 PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
-
-
- /* 3:7.0 PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
-
- /* PCI Slot 3 (if active riser) */
- if(bus_pxhd_3) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
- }
-
- /* PCI Slot 4 (if active riser) */
- if(bus_pxhd_4) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
- }
-
- /* Onboard SCSI 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
-
- /* Onboard SCSI 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
-
- /* Onboard NIC 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
-
- /* Onboard NIC 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
-
- /* Onboard VGA */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c
deleted file mode 100644
index 0ac526f0ee..0000000000
--- a/src/mainboard/intel/jarrell/power_reset_check.c
+++ /dev/null
@@ -1,22 +0,0 @@
-void full_reset(void)
-{
- /* Enable power on after power fail... */
- unsigned byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- byte &= 0xfe;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
-
- outb(0x0e, 0xcf9);
-}
-
-static void power_down_reset_check(void)
-{
- uint8_t cmos;
-
- cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
- print_debug("Boot byte = ");
- print_debug_hex8(cmos);
- print_debug("\n");
-
- if((cmos>2)&&(cmos&1)) full_reset();
-}
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
deleted file mode 100644
index fb4d4834f9..0000000000
--- a/src/mainboard/intel/jarrell/romstage.c
+++ /dev/null
@@ -1,110 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include "southbridge/intel/i82801ex/early_smbus.c"
-#include "northbridge/intel/e7520/raminit.h"
-#include "superio/nsc/pc87427/pc87427.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "watchdog.c"
-#include "southbridge/intel/i82801ex/reset.c"
-#include "power_reset_check.c"
-#include "jarrell_fixups.c"
-#include "superio/nsc/pc87427/early_init.c"
-#include "northbridge/intel/e7520/memory_initialized.c"
-#include "cpu/x86/bist.h"
-#include <spd.h>
-#include "lib/debug.c" // XXX
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
-#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
-#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
-
-#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/e7520/raminit.c"
-#include "lib/generic_sdram.c"
-#include "arch/x86/lib/stages.c"
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
- static const struct mem_controller mch[] = {
- {
- .node_id = 0,
- .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
- .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
- }
- };
-
- if (bist == 0) {
- /* Skip this if there was a built in self test failure */
- early_mtrr_init();
- if (memory_initialized())
- skip_romstage();
- }
-
- /* Setup the console */
- pc87427_disable_dev(CONSOLE_SERIAL_DEV);
- pc87427_disable_dev(HIDDEN_SERIAL_DEV);
- pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
- /* Enable Serial 2 lines instead of GPIO */
- outb(0x2c, 0x2e);
- outb((inb(0x2f) & (~1<<1)), 0x2f);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
-
- pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
- xbus_cfg(PC87427_XBUS_DEV);
-
- /* MOVE ME TO A BETTER LOCATION !!! */
- /* config LPC decode for flash memory access */
- device_t dev;
- dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID)
- die("Missing ich5?");
- pci_write_config32(dev, 0xe8, 0x00000000);
- pci_write_config8(dev, 0xf0, 0x00);
-
-#if 0
- print_pci_devices();
-#endif
- enable_smbus();
-#if 0
-// dump_spd_registers(&cpu[0]);
- int i;
- for(i = 0; i < 1; i++)
- dump_spd_registers();
-#endif
- disable_watchdogs();
- power_down_reset_check();
-// dump_ipmi_registers();
- mainboard_set_e7520_leds();
- sdram_initialize(ARRAY_SIZE(mch), mch);
- ich5_watchdog_on();
-#if 0
- dump_pci_devices();
- dump_pci_device(PCI_DEV(0, 0x00, 0));
- dump_bar14(PCI_DEV(0, 0x00, 0));
-#endif
- /* NOTE: ROMCC dies with an internal compiler error if the
- * following line is removed.
- */
- print_debug("SDRAM is up.\n");
-}
diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c
deleted file mode 100644
index 7f7a039068..0000000000
--- a/src/mainboard/intel/jarrell/watchdog.c
+++ /dev/null
@@ -1,139 +0,0 @@
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-
-#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
-#define NSC_WDBASE 0x600
-#define ICH5_WDBASE 0x400
-#define ICH5_GPIOBASE 0x500
-
-static void disable_sio_watchdog(device_t dev)
-{
- /* FIXME move me somewhere more appropriate */
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 1);
- pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
- /* disable the sio watchdog */
- outb(0, NSC_WDBASE + 0);
- pnp_set_enable(dev, 0);
-}
-
-static void disable_ich5_watchdog(void)
-{
- /* FIXME move me somewhere more appropriate */
- device_t dev;
- unsigned long value, base;
- dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
- die("Missing ich5?");
- }
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
-
- /* Set and enable acpibase */
- pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
- pci_write_config8(dev, 0x44, 0x10);
- base = ICH5_WDBASE + 0x60;
-
- /* Set bit 11 in TCO1_CNT */
- value = inw(base + 0x08);
- value |= 1 << 11;
- outw(value, base + 0x08);
-
- /* Clear TCO timeout status */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
-}
-
-static void disable_jarell_frb3(void)
-{
- device_t dev;
- unsigned long value, base;
- dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
- die("Missing ich5?");
- }
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 0);
- pci_write_config16(dev, 0x04, value);
-
- /* Set gpio base */
- pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
- base = ICH5_GPIOBASE;
-
- /* Enable GPIO Bar */
- value = pci_read_config32(dev, 0x5c);
- value |= 0x10;
- pci_write_config32(dev, 0x5c, value);
-
- /* Configure GPIO 48 and 40 as GPIO */
- value = inl(base + 0x30);
- value |= (1 << 16) | ( 1 << 8);
- outl(value, base + 0x30);
-
- /* Configure GPIO 48 as Output */
- value = inl(base + 0x34);
- value &= ~(1 << 16);
- outl(value, base + 0x34);
-
- /* Toggle GPIO 48 high to low */
- value = inl(base + 0x38);
- value |= (1 << 16);
- outl(value, base + 0x38);
- value &= ~(1 << 16);
- outl(value, base + 0x38);
-
-}
-
-static void disable_watchdogs(void)
-{
- disable_sio_watchdog(NSC_WD_DEV);
- disable_ich5_watchdog();
- disable_jarell_frb3();
- print_debug("Watchdogs disabled\n");
-}
-
-static void ich5_watchdog_on(void)
-{
- device_t dev;
- unsigned long value, base;
- unsigned char byte;
-
- /* check cmos options */
- byte = cmos_read(RTC_BOOT_BYTE-1);
- if(!(byte & 1)) return; /* no boot watchdog */
- byte = cmos_read(RTC_BOOT_BYTE);
- if(!(byte & 2)) return; /* fallback so ignore */
-
- dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
- die("Missing ich5?");
- }
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
-
- /* Set and enable acpibase */
- pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
- pci_write_config8(dev, 0x44, 0x10);
- base = ICH5_WDBASE + 0x60;
-
- /* Clear TCO timeout status */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
-
- /* set the time value 1 cnt = .6 sec */
- outw(0x0010, base + 0x01);
- /* reload the timer with the value */
- outw(0x0001, base + 0x00);
-
- /* clear bit 11 in TCO1_CNT to start watchdog */
- value = inw(base + 0x08);
- value &= ~(1 << 11);
- outw(value, base + 0x08);
-
- print_debug("Watchdog ICH5 enabled\n");
-}