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-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb2
3 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index a8e835e95c..8751255076 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -131,8 +131,6 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root ports.
# PCIE Port 1 x4 -> SLOT1
register "PcieRpEnable[0]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
index 5c41f22d8a..f07d38199f 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
@@ -132,8 +132,6 @@ chip soc/intel/skylake
.voltage_limit = 0x0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root ports.
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
index 2a2d761af1..0057a288a4 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
@@ -128,8 +128,6 @@ chip soc/intel/skylake
.voltage_limit = 0x0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root port.
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"