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-rw-r--r--src/mainboard/intel/leafhill/variants/pyro/memory.c114
1 files changed, 0 insertions, 114 deletions
diff --git a/src/mainboard/intel/leafhill/variants/pyro/memory.c b/src/mainboard/intel/leafhill/variants/pyro/memory.c
deleted file mode 100644
index 71ee060610..0000000000
--- a/src/mainboard/intel/leafhill/variants/pyro/memory.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <gpio.h>
-#include <soc/meminit.h>
-#include <variant/gpio.h>
-
-
-static const struct lpddr4_sku skus[] = {
- /*
- * K4F6E304HB-MGCJ - both logical channels While the parts
- * are listed at 16Gb there are 2 ranks per channel so indicate
- * the deneisty as 8Gb per rank.
- */
- [0] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .ch0_dual_rank = 1,
- .ch1_dual_rank = 1,
- .part_num = "K4F6E304HB-MGCJ",
- },
- /* K4F8E304HB-MGCJ - both logical channels */
- [1] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .part_num = "K4F8E304HB-MGCJ",
- },
- /*
- * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
- * are listed at 16Gb there are 2 ranks per channel so indicate
- * the deneisty as 8Gb per rank.
- */
- [2] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .ch0_dual_rank = 1,
- .ch1_dual_rank = 1,
- .part_num = "MT53B512M32D2NP",
- .disable_periodic_retraining = 1,
- },
- /* MT53B256M32D1NP-062 WT:C - both logical channels */
- [3] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .part_num = "MT53B256M32D1NP",
- .disable_periodic_retraining = 1,
- },
- /*
- * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
- * are listed at 16Gb there are 2 ranks per channel so indicate the
- * density as 8Gb per rank.
- */
- [4] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .ch0_dual_rank = 1,
- .ch1_dual_rank = 1,
- .part_num = "H9HCNNNBPUMLHR",
- },
- /* H9HCNNN8KUMLHR-NLE - both logical channels */
- [5] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .part_num = "H9HCNNN8KUMLHR",
- },
- /* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */
- [0xe] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .ch0_dual_rank = 1,
- .ch1_dual_rank = 1,
- .part_num = "K4F6E304HB-MGCH",
- },
- /* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */
- [0xf] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .ch0_dual_rank = 0,
- .ch1_dual_rank = 0,
- .part_num = "K4F8E304HB-MGCH",
- },
-};
-
-static const struct lpddr4_cfg lp4cfg = {
- .skus = skus,
- .num_skus = ARRAY_SIZE(skus),
- .swizzle_config = &baseboard_lpddr4_swizzle,
-};
-
-const struct lpddr4_cfg *variant_lpddr4_config(void)
-{
- return &lp4cfg;
-}