1 files changed, 0 insertions, 67 deletions
diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig
deleted file mode 100644
index b5a57b798b..0000000000
--- a/src/mainboard/intel/littleplains/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_LITTLEPLAINS
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select NORTHBRIDGE_INTEL_FSP_RANGELEY
-	select SOUTHBRIDGE_INTEL_FSP_RANGELEY
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-
-config MAINBOARD_DIR
-	string
-	default intel/littleplains
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Little Plains"
-
-config MAX_CPUS
-	int
-	default 16
-
-config CBFS_SIZE
-	hex
-	default 0x400000
-
-config ENABLE_FSP_FAST_BOOT
-	bool
-	depends on HAVE_FSP_BIN
-	default y
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config UART_FOR_CONSOLE
-	int
-	default 1
-	help
-	  The Little Plains board uses COM2 (2f8) for the serial console.
-
-config PAYLOAD_CONFIGFILE
-	string
-	depends on PAYLOAD_SEABIOS
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
-	help
-	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
-	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
-	  we put the SeaBIOS buffer area down in the 0x9000 segment.
-
-endif # BOARD_INTEL_LITTLEPLAINS