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-rw-r--r--src/mainboard/intel/saddlebrook/Kconfig1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb5
2 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index 524bcca011..f2b7344aaa 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
select SADDLEBROOK_USES_FSP1_1
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
+ select USE_INTEL_FSP_MP_INIT
config SADDLEBROOK_USES_FSP1_1
bool "FSP driver 1.1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 8f78249b3b..2f84a5dde5 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -140,11 +140,6 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
- # Skip coreboot MP Init
- register "common_soc_config" = "{
- .use_fsp_mp_init = 1,
- }"
-
# Enable x1 slot
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"