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Diffstat (limited to 'src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb')
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index beaf8fd1ec..55d250539c 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -14,8 +14,7 @@ chip soc/intel/alderlake
# TCSS
register "TcssAuxOri" = "1"
- register "IomTypeCPortPadCfg[0]" = "0x09020005"
- register "IomTypeCPortPadCfg[1]" = "0x09020006"
+ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
# Enable heci communication
register "HeciEnabled" = "1"