diff options
Diffstat (limited to 'src/mainboard/intel/truxton/Options.lb')
| -rw-r--r-- | src/mainboard/intel/truxton/Options.lb | 138 |
1 files changed, 69 insertions, 69 deletions
diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb index d4c777c4e2..48160b42f4 100644 --- a/src/mainboard/intel/truxton/Options.lb +++ b/src/mainboard/intel/truxton/Options.lb @@ -17,56 +17,56 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -74,14 +74,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE = 2 * 1024 * 1024 +default CONFIG_ROM_SIZE = 2 * 1024 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -93,19 +93,19 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=1 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code for SMP support @@ -123,39 +123,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Truxton" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 +default CONFIG_MAINBOARD_PART_NUMBER="Truxton" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 ### ### Coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -186,21 +186,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -212,17 +212,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb |