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-rw-r--r--src/mainboard/intel/dcp847ske/Makefile.inc1
-rw-r--r--src/mainboard/intel/dcp847ske/early_southbridge.c3
-rw-r--r--src/mainboard/intel/emeraldlake2/Makefile.inc2
-rw-r--r--src/mainboard/intel/emeraldlake2/early_init.c (renamed from src/mainboard/intel/emeraldlake2/romstage.c)3
4 files changed, 7 insertions, 2 deletions
diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc
index ec86d8455d..28bc7c7cc9 100644
--- a/src/mainboard/intel/dcp847ske/Makefile.inc
+++ b/src/mainboard/intel/dcp847ske/Makefile.inc
@@ -1,3 +1,4 @@
+bootblock-y += early_southbridge.c
romstage-y += early_southbridge.c
bootblock-y += gpio.c
romstage-y += gpio.c
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 8f38270388..53f5564a97 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <stdint.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
@@ -160,7 +161,7 @@ static void superio_init(void)
SUPERIO_LOCK;
}
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
{
superio_init();
hwm_init();
diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc
index 974241dcc2..3e78db075b 100644
--- a/src/mainboard/intel/emeraldlake2/Makefile.inc
+++ b/src/mainboard/intel/emeraldlake2/Makefile.inc
@@ -17,3 +17,5 @@ romstage-y += chromeos.c
ramstage-y += chromeos.c
bootblock-y += gpio.c
romstage-y += gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 2cfb5569fb..94a46550b2 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -43,7 +44,7 @@ void mainboard_pch_lpc_setup(void)
}
}
-void mainboard_config_superio(void)
+void bootblock_mainboard_early_init(void)
{
const u16 port = SIO_PORT;
const u16 runtime_port = 0x180;