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-rw-r--r--src/mainboard/intel/d945gclf/romstage.c2
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index bac2a0bc96..1441bb5597 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -216,9 +216,7 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
-#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
#include <cbmem.h>
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index d928de5c56..4a04b9a091 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -121,9 +121,7 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i3100/cmos_failover.c"
-#endif
void early_config(void) {
device_t dev;