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-rw-r--r--src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb2
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb3
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb3
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb3
-rw-r--r--src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb3
-rw-r--r--src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb3
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb3
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb3
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb3
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
12 files changed, 0 insertions, 35 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index 818f32f9fa..73055010ca 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -13,8 +13,6 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration
- # Enable Speed Shift Technology/HWP support
- register "speed_shift_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index e10059887e..1110bc1e32 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -60,9 +60,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index bf7aa1e962..42023149a9 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -57,9 +57,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
index 0b40a5c359..12b1c47f33 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -43,9 +43,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Disable S0ix
register "s0ix_enable" = "0"
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
index 49303da030..1215628dbc 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/icelake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
index a1c32c99be..e8c6e8f5c4 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/icelake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index b9aec378fb..61a5e70695 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -122,9 +122,6 @@ chip soc/intel/jasperlake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 8de089de90..e17c8b71f3 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -16,9 +16,6 @@ chip soc/intel/skylake
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 3afff4506e..07afb7bd1b 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -17,9 +17,6 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index a25cb8c579..5c64326e3e 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -14,9 +14,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 09ab2583c1..de93c99aa2 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -115,9 +115,6 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable S0ix
register "s0ix_enable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 25c229332a..4078894bfd 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -119,9 +119,6 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable S0ix
register "s0ix_enable" = "1"