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-rw-r--r--src/mainboard/intel/d945gclf/devicetree.cb2
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c15
-rw-r--r--src/mainboard/intel/dg41wv/devicetree.cb2
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c15
4 files changed, 6 insertions, 28 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index c01465c4e7..7114a29a83 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -52,6 +52,8 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
+ register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
+
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe port 1
device pci 1c.1 off end # PCIe port 2
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f0ae18823e..ba01379548 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -28,19 +28,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
-static void ich7_enable_lpc(void)
-{
- // Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
- // Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
- // Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
- | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
- // Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);
-}
-
static void rcba_config(void)
{
/* Set up virtual channel 0 */
@@ -98,7 +85,7 @@ void mainboard_romstage_entry(void)
enable_lapic();
- ich7_enable_lpc();
+ i82801gx_lpc_setup();
/* Enable SuperIO PM */
lpc47m15x_enable_serial(PME_DEV, 0x680);
lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb
index 295fbc4f38..c00e998bcc 100644
--- a/src/mainboard/intel/dg41wv/devicetree.cb
+++ b/src/mainboard/intel/dg41wv/devicetree.cb
@@ -65,6 +65,8 @@ chip northbridge/intel/x4x # Northbridge
register "ide_enable_primary" = "0x1"
register "gpe0_en" = "0x440"
+ register "gen1_dec" = "0x00fc0a01" # HWM
+
device pci 1b.0 on # Audio
subsystemid 0x8086 0x5756
end
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index a6969ad4d2..c0127b6c45 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -56,19 +56,6 @@ static void mb_lpc_setup(void)
ich7_setup_cir();
}
-static void ich7_enable_lpc(void)
-{
- pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
- /* Fixed IO decode ranges */
- pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
- /* LPC enable devices */
- pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
- | COMB_LPC_EN | COMA_LPC_EN);
- /* IO decode range: HWM on 0xa00 */
- pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
-}
-
void mainboard_romstage_entry(void)
{
// ch0 ch1
@@ -77,7 +64,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
- ich7_enable_lpc();
+ i82801gx_lpc_setup();
mb_lpc_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);