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-rw-r--r--src/mainboard/intel/cedarisland_crb/ramstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
new file mode 100644
index 0000000000..f4c716eda2
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+ /* configure Lewisburg PCH GPIO controller after FSP-M */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}