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-rw-r--r--src/mainboard/intel/d945gclf/romstage.c26
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c6
2 files changed, 2 insertions, 30 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index bad2b6d538..f6fc8df2f4 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -89,31 +89,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(0x3410);
- reg32 |= (1 << 6);
- RCBA32(0x3410) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 74f86221eb..81d50670e9 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -32,7 +32,6 @@
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -55,10 +54,7 @@ static void mb_lpc_setup(void)
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)